Scalable integrated mim capacitor using gate metal
Abstract
According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps.
Claims
exact text as granted — not AI-modified1 - 20 . (canceled)
21 . An integrated capacitor comprising:
first and second coplanar gate metal terminals formed on a substrate and separated by a filler, said filler including at least one metal contact bar; and at least one contact formed on at least one of said first and second coplanar gate metal terminals, said metal contact bar extending in a longitudinal direction for a length less than a length of the first or second coplanar gate metal terminals, wherein said at least one contact is formed at a position in the longitudinal direction on the at least one of said first and second substantially coplanar gate metal terminals that is beyond an end of said at least one metal contact bar.
22 . The integrated capacitor of claim 21 , wherein at least one of the filler, the first coplanar gate metal terminal and the second coplanar gate metal terminal is formed in an isolation region of the substrate.
23 . The integrated capacitor of claim 21 , wherein the filler includes:
at least one spacer; at least one etch-stop filler segment, and said at least one metal contact bar, said at least one etch-stop filler segment, said at least one spacer and at least one of said first and second coplanar gate metal terminals are configured to produce a capacitance of the integrated capacitor.
24 . The integrated capacitor of claim 23 , wherein the at least one metal contact bar is formed in the at least one etch-stop filler segment, and said at least one spacer is formed between said at least one metal contact bar and one of the first and second coplanar gate metal terminals.
25 . The integrated capacitor of claim 21 , further comprising:
a transistor gate stack formed with said integrated capacitor, wherein at least one of the first and second coplanar gate metal terminals include a metal configured to include a metal gate of the transistor gate stack.
26 . The integrated capacitor of claim 21 , wherein the first coplanar gate metal terminal includes a first metal and the second coplanar gate metal terminal includes a second metal different from the first metal.
27 . A method of manufacturing an integrated capacitor, comprising:
forming first and second coplanar gate metal terminals on a substrate forming a filler separating the first and second coplanar gate metal terminals, said filler including at least one metal contact bar; and forming at least one contact on at least one of said first and second coplanar gate metal terminals, said metal contact bar extending in a longitudinal direction for a length less than a length of the first or second coplanar gate metal terminals, wherein said at least one contact is formed at a position in the longitudinal direction on the at least one of said first and second substantially coplanar gate metal terminals that is beyond an end of said at least one metal contact bar.
28 . The method of claim 27 , wherein said first and second coplanar gate metal terminals are formed by a dummy-material replacement process that includes:
forming first and second dummy-material segments on the substrate; removing the first and second dummy-material segments from the substrate; and forming the first and second coplanar gate metal terminals on the substrate in positions of the first and second dummy-material segments.
29 . The method of claim 27 , wherein at least one of the filler, the first coplanar gate metal terminal and the second coplanar gate metal terminal is formed in an isolation region of the substrate.
30 . The method of claim 27 , wherein the forming of the filler includes:
forming at least one spacer in the filler; and forming at least one etch-stop filler segment in the filler, wherein the at least one metal contact bar, the at least one etch-stop filler segment, the at least one spacer and at least one of the first and second coplanar gate metal terminals are configured to produce a capacitance of the integrated capacitor.
31 . The method of claim 30 , wherein the at least one metal contact bar is formed in the at least one etch-stop filler segment, and the at least one spacer is formed between the at least one metal contact bar and one of the first and second coplanar gate metal terminals.
32 . The method of claim 27 , further comprising:
forming a transistor gate stack with the integrated capacitor, wherein at least one of the first and second coplanar gate metal terminals is configured to include a metal that includes a gate metal of the transistor gate stack.
33 . The method of claim 27 , wherein the first coplanar gate metal terminal includes a first metal and the second coplanar gate metal terminal includes a second metal different from the first metal.
34 . An integrated circuit (IC), comprising:
at least one device; and at least one integrated capacitor that includes
first and second coplanar gate metal terminals formed on a substrate and separated by a filler, said filler including at least one metal contact bar, and
at least one contact formed on at least one of said first and second coplanar gate metal terminals, said metal contact bar extending in a longitudinal direction for a length less than a length of the first or second coplanar gate metal terminals,
wherein said at least one contact is formed at a position in the longitudinal direction on the at least one of said first and second substantially coplanar gate metal terminals that is beyond an end of said at least one metal contact bar.
35 . The IC of claim 34 , wherein at least one of the filler, the first coplanar gate metal electrode and the second coplanar gate metal terminals is formed on an isolation region of the substrate.
36 . The IC of claim 34 , wherein the filler includes:
at least one spacer, and at least one etch-stop filler segment, wherein the at least one metal contact bar, the at least one etch-stop filler segment, the at least one spacer, and at least one of the first and second coplanar gate metal terminals is configured to produce a capacitance of the integrated capacitor.
37 . The IC of claim 36 , wherein the at least one metal contact bar is formed in the at least one etch-stop filler segment, and the at least one spacer is formed between the at least one metal contact bar and one of the first and second coplanar gate metal terminals.
38 . The IC of claim 34 , further comprising:
a transistor gate stack formed with the IC, at least one of the first and second coplanar gate metal terminals including a metal that includes a metal gate of the transistor gate stack.
39 . The IC of claim 34 , wherein the first coplanar gate metal terminal includes a first metal and the second coplanar gate metal terminal includes a second metal different from the first metal.
40 . The integrated capacitor of claim 21 , wherein the at least one contact is formed at a position in a height direction that is below an upper contact surface of the at least one metal contact bar.
41 . The integrated capacitor of claim 40 , wherein the at least one contact is substantially coplanar in the height direction with an upper surface of the filler, and the at least one metal contact bar extends in the height direction beyond the upper surface of the filler.Join the waitlist — get patent alerts
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