Double patterning method to form sub-lithographic pillars

Abstract

A method and resulting structure, is disclosed to fabricate vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a at least one dimension below the minimum lithographical resolution, F, of the lithographic technique employed. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.

1 . A structure of vertical bipolar junction transistors, the structure comprising:
 a regular array of base contact pillars and a regular array of emitter contact pillars, the base contact pillars and the emitter contact pillars each having a width below a minimum lithographical resolution, F;   a first level base contact plug in electrical contact with a plurality of the base contact pillars; and   a storage element located above the regular array of base contact pillars and the regular array of emitter contact pillars.   
     
     
         2 . The structure of  claim 1 , wherein the storage element is a phase change storage element. 
     
     
         3 . The structure of  claim 1 , wherein the storage element is located below a word line. 
     
     
         4 . The structure of  claim 1 , further comprising a first level emitter contact in electrical contact with a single emitter contact pillar. 
     
     
         5 . A system, comprising:
 a controller; and   a memory array including:
 a phase change memory cell; 
 a regular array of base contact pillars and a regular array of emitter contact pillars, the base contact pillars and the emitter contact pillars each having a width below a minimum lithographical resolution, F; and 
 a first level base contact plug in electrical contact with a plurality of the base contact pillars. 
   
     
     
         6 . The system of  claim 5 , wherein the regular array of base contact pillars and the regular array of emitter contact pillars share a common collector. 
     
     
         7 . The system of  claim 5 , wherein the regular array of base contact pillars and the regular array of emitter contact pillars are defined by a first set of parallel trenches in a first direction and a second set of parallel trenches in a second direction that is approximately perpendicular to the first direction. 
     
     
         8 . The system of  claim 5 , wherein the base contact pillars and the emitter contact pillars have a width of about F/2. 
     
     
         9 . The system of  claim 5 , wherein each row of the emitter contact pillars is separated from an adjacent row by a shallow trench isolation region. 
     
     
         10 . The system of  claim 5 , wherein each row of the emitter contact pillars is separated from an adjacent row by a shallow trench isolation region. 
     
     
         11 . The system of  claim 5 , further comprising:
 a first region having a dopant of a first polarity; and   a second region having a dopant of a second polarity, the second region being formed over the first region.   
     
     
         12 . The system of  claim 11 , further comprising:
 a first plurality of shallow trench isolation regions extending to the first region; and   a second plurality of shallow trench isolation regions extending at least to an uppermost portion of the second region but not as far as the first region.   
     
     
         13 . The system of  claim 5 , wherein the regular array of base contact pillars and a regular array of emitter contact pillars each have a pitch of about F. 
     
     
         14 . A device, comprising:
 a structure of vertical bipolar transistors having a regular array including a plurality of base contact pillars and a plurality emitter contact pillars, the plurality of base contact pillars and the plurality of emitter contact pillars each having a width below a minimum lithographical resolution;   a first level base contact plug in electrical contact with each of the plurality of the base contact pillars; and   a storage element coupled to the regular array of the base contact pillars and the emitter contact pillars.   
     
     
         15 . The device of  claim 14 , wherein the storage element comprises a plurality of phase change memory elements, and ones of the vertical bipolar transistors are coupled to respective ones of the plurality of phase change memory elements, the vertical bipolar transistors being configured as switching elements for the respective ones of the plurality of phase change memory elements. 
     
     
         16 . The device of  claim 14 , wherein the plurality of base contact pillars include a first set of shallow trench isolation regions that extend at least to a first doped region, and the plurality of emitter contact pillars include a second set of shallow trench isolation regions which do not extend to the first doped region. 
     
     
         17 . The device of  claim 16 , wherein the first doped region is a common collector, and the second set of shallow trench isolation regions are formed substantially perpendicular to the first set of shallow trench isolation regions. 
     
     
         18 . A method of fabricating an electronic device, the method comprising:
 forming an array of base contact pillars and an array of emitter contact pillars, the forming of the array of base contact pillars and the array of the emitter contact pillars including a double-patterning technique including
 forming a first set of shallow trench isolation regions extending at least to a first doped region, and 
 forming a second set of shallow trench isolation regions which do not extend to the first doped region, the first doped region being a common collector, the second set of shallow trench isolation regions being formed substantially perpendicular to the first set of shallow trench isolation regions. 
   
     
     
         19 . The method of  claim 18 , wherein the second set of shallow trench isolation regions extend to a second doped region, the second doped region having a polarity opposite that of the first doped region. 
     
     
         20 . The method of  claim 18 , further comprising forming the base contact pillars and the emitter contact pillars to each have a width of about F/2, where F is a minimum lithographical resolution of a lithographic system used to form the electronic device. 
     
     
         21 . The method of  claim 18 , wherein the double-patterning technique further includes:
 partially removing a dielectric material from between a patterned etch stop layer after filling each set of shallow trench isolation regions with the dielectric material; and   removing the patterned etch stop layer after partially removing the dielectric material from between the patterned etch stop layer.   
     
     
         22 . The method of  claim 18 , further comprising forming a storage element above the array of base contact pillars and the array of emitter contact pillars.