Merged fin finfet with (100) sidewall surfaces and method of making same

Abstract

A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.

What is claimed is: 
     
         1 . A structure, comprising:
 two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of said two or more find being a solid rectangular block of single-crystal semiconductor material, each fin of said two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of said two or more fins are (100) surfaces and the longitudinal axes of said two or more fins aligned with a [100] direction;   a gate dielectric layer on each fin of said two or more fins;   an electrically conductive gate over said gate dielectric layer over said central region of each fin of said of two or more fins; and   a merged source/drain comprising a continuous layer of an epitaxial semiconductor material on ends each fin of said two or more fins, said ends on a same side of said conductive gate, wherein a top surface of said merged source/drain has no (111) facets.   
     
     
         2 . The structure of  claim 1 , wherein a width of each fin of said two or more fins is about 30 nm or less and spaces between said two or more fins are about 30 nm or less. 
     
     
         3 . The structure of  claim 1 , wherein a width of each fin of said two or more fins is between about 5 nm and about 40 nm. 
     
     
         4 . The structure of  claim 1 , wherein spaces between each fin of said two or more fins is between about is between about 8 nm and about 30 nm. 
     
     
         5 . The structure of  claim 1 , wherein said two or more single-crystal silicon fins are Si, SiGe or Si:C. 
     
     
         6 . The structure of  claim 1 , wherein said semiconductor substrate and said two or more single-crystal silicon fins are both Si and said epitaxial semiconductor material is SiGe. 
     
     
         7 . The structure of  claim 1 , wherein said semiconductor substrate and said two or more single-crystal silicon fins are both Si and said epitaxial semiconductor material is selected from the group consisting of Si, SiGe, and Si:C. 
     
     
         8 . The structure of  claim 1 , wherein said gate dielectric comprises material having a relative permittivity above about 10 and selected from the group consisting of metal oxides, Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , metal silicates, HfSi x O y  or HfSi x O y N z  and combinations thereof. 
     
     
         9 . The structure of  claim 1 , further including:
 a dielectric cap on top surfaces of each fin of said two or more fins, said gate dielectric layer on exposed surfaces of said dielectric cap.   
     
     
         10 . The structure of  claim 1 , wherein said merged source/drain is doped N-type or P-type. 
     
     
         11 . The structure of  claim 1 , wherein said two or more fins each have a width of about 30 nm or less and atop surface of said merged source/drain is smooth and uniform and has no divots. 
     
     
         12 . The structure of  claim 1 , wherein said two or more fins are comprised of an upper single-crystal semiconductor layer of a semiconductor on insulator wafer comprising said insulating layer between a semiconductor substrate and said upper single-crystal semiconductor layer. 
     
     
         13 . The structure of  claim 1 , wherein said two or more fins are comprised of an upper single-crystal silicon layer of silicon on insulator wafer comprising said insulating layer between a single-crystal silicon substrate and said upper single-crystal silicon layer. 
     
     
         14 . The structure of  claim 1 , wherein said gate dielectric layer is only on top surfaces of said central regions of each fin of said two or more fins and on opposite sidewall regions of said central regions of each fin of said two or more fins. 
     
     
         15 . The structure of  claim 1 , including a dielectric cap on top surfaces of said central regions of each fin of said two or more fins. 
     
     
         16 . The structure of  claim 1 , including:
 dielectric caps on top surfaces of said central regions of each fin of said two or more fins; and   said gate dielectric layer only on said dielectric caps and opposite sidewall regions said central regions of each fin of said two or more fins.