US2015102418A1PendingUtilityA1

Semiconductor device and method for manufacturing the device

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: May 14, 2012Filed: Dec 19, 2014Published: Apr 16, 2015
Est. expiryMay 14, 2032(~5.8 yrs left)· nominal 20-yr term from priority
Inventors:Ju-Youn Kim
H10D 64/691H10D 64/685H10D 84/0181H10D 84/0177H10D 84/853H10D 84/0193H10D 84/85H10D 84/038H10D 64/68H10D 64/01H01L 27/1104H01L 29/51H01L 27/0924H10B 10/12
52
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A static random access memory (SRAM) device comprising: a N-type field effect transistor comprising: a high dielectric constant (high-k) layer disposed on a substrate, a diffusion layer including a metal oxide disposed on the high-k layer, a passivation layer disposed on the diffusion layer, and a first metal gate disposed on the passivation layer; and a P-type field effect transistor comprising: the high-k layer disposed on the substrate. 
     
     
         2 . The SRAM device of  claim 1 , wherein the P-type field effect transistor further comprising; a diffusion barrier layer formed on the second high-k layer; the diffusion layer disposed on the diffusion barrier layer; the passivation layer disposed on the diffusion layer; and a second metal gate disposed on the passivation layer, wherein the diffusion barrier layer prevents metal atoms of the diffusion layer from being diffused into the high-k layer. 
     
     
         3 . The SRAM device of  claim 1 , wherein the first metal gate includes a first plurality of conductive layers and the second metal gate includes a second plurality of conductive layers, wherein first plurality of conductive layers include a conductive layer different from that of the second plurality of conductive layers. 
     
     
         4 . The SRAM device of  claim 1 , wherein the N-type field effect transistor and the P-type field effect transistor is configured to be a fin-type transistor.

Join the waitlist — get patent alerts

Track US2015102418A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.