Methods for dicing a compound semiconductor wafer, and diced wafers and die obtained thereby

Abstract

Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.

What is claimed is: 
     
         1 . A compound semiconductor die diced from a compound semiconductor wafer by a plasma etch dicing process in such a way that a known spatial relationship is created between at least one side wall of the die and at least one optical element formed on or in a surface of the die, and wherein the known spatial relationship between said at least one side wall and said at least one element allows said at least one side wall to be used as a passive alignment feature such that aligning said at least one side wall with a first alignment feature extending upwardly from a top surface of an external device results in alignment of said at least one optical element with the external device. 
     
     
         2 . The compound semiconductor die of  claim 1 , wherein the die has a shape of a rectangle. 
     
     
         3 . The compound semiconductor die of  claim 1 , wherein:
 the plasma etch dicing process that is used to dice the wafer provides the die with at least first and second side walls that have known spatial relationships to said at least one optical element and to one another, and   the known spatial relationships allow the first and second side walls to be used as passive alignment features such that aligning the first side wall with the first alignment feature of the external device and aligning the second side wall with a second alignment feature extending upwardly from the top surface of the external device results in alignment of the external device with said at least one optical element.   
     
     
         4 . The compound semiconductor die of  claim 3 , wherein the external device is an alignment base, and wherein the first and second alignment features each further include a first sidewall and second sidewall forming a right angle and the first alignment feature and second alignment feature are positioned on the top surface of the alignment base so as to receive the first die. 
     
     
         5 . The compound semiconductor die of  claim 4 , wherein the alignment base is configured to be aligned with a second external structure such that the alignment of said at least one optical element with the alignment base results in alignment of said at least one optical element with the second external structure. 
     
     
         6 . The compound semiconductor die of  claim 3 , wherein the first and second side walls are substantially perpendicular to one another, and wherein said at least one optical element is formed on or in a surface of the die that is substantially perpendicular to the first and second side walls. 
     
     
         7 . The compound semiconductor die of  claim 3 , wherein the die has a shape of a rectangle, and wherein the first and second side walls are substantially parallel to one another and substantially perpendicular to said surface. 
     
     
         8 . The compound semiconductor die of  claim 1 , wherein the die has a non-rectangular shape. 
     
     
         9 . The compound semiconductor die of  claim 1 , wherein the die is a laser diode die and wherein said at least one optical element is a light-emitting facet of the die. 
     
     
         10 . The compound semiconductor die of  claim 1 , wherein the die is a photodiode die and wherein said at least one optical element is a light-receiving facet of the die. 
     
     
         11 . The compound semiconductor die of  claim 1 , wherein the external device is an alignment base and the first alignment feature further includes a first sidewall and a second sidewall forming a right angle configured to receive the die. 
     
     
         12 . An array of compound semiconductor (CS) dies, wherein the CS dies have been diced from one or more CS wafers by a plasma etch dicing process that provides each CS die with at least one side wall that has a known spatial relationship to at least one optical element formed on or in a surface of the respective CS die, and wherein the known spatial relationships allow the respective side walls to be used as respective alignment features such that aligning the respective side walls of the respective CS dies with one another results in alignment of the respective optical elements of the respective CS dies with one another. 
     
     
         13 . The array of  claim 12 , wherein at least two of the CS dies of the array have different dimensions. 
     
     
         14 . The array of  claim 12 , wherein at least two of the CS dies of the array have different shapes. 
     
     
         15 . The array of  claim 12 , wherein at least two of the CS dies have different functions. 
     
     
         16 . The array of  claim 12 , wherein at least two of the CS dies are laser diode dies having different operating wavelengths. 
     
     
         17 . The array of  claim 12 , wherein at least two of the CS dies are photodiode dies having different operating wavelengths. 
     
     
         18 . The array of  claim 12 , wherein at least one of the CS dies is laser diode die and at least one of the CS dies is a photodiode, and wherein said optical element of the laser diode is a light-emitting facet and wherein said optical element of the photodiode is a light-receiving facet. 
     
     
         19 . The array of  claim 12 , wherein at least two of the CS dies have been diced from different CS wafers and are made of different materials. 
     
     
         20 . The array of  claim 12 , wherein at least two of the CS dies have been diced from a same CS wafer and are made of a same material.