Method and structure of forming backside through silicon via connections

Abstract

A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.

What is claimed is: 
     
         1 . A structure comprising:
 a substrate having a backside;   a first through silicon via having sides, a bottom surface, and a first height protruding from the backside of the substrate; and   a first conductor facing the backside of the substrate and in electrical contact with the first silicon via;   wherein a first via liner encapsulates the sides and the bottom surface of the first through silicon via.   
     
     
         2 . The structure of  claim 1 , wherein the first conductor has a first conductor liner; and wherein the first conductor liner is in direct contact with the first via liner on the bottom surface of the first through silicon via. 
     
     
         3 . The structure of  claim 2 , wherein the first conductor is a redistribution line. 
     
     
         4 . The structure of  claim 2 , wherein the first via liner comprises a tantalum layer and a tantalum nitride layer. 
     
     
         5 . The structure of  claim 4 , wherein the conductor liner comprises a tantalum layer and a tantalum nitride layer. 
     
     
         6 . The structure of  claim 1 , further comprising a second through silicon via having a second height, wherein the first and second heights are different. 
     
     
         7 . The structure of  claim 6 , wherein a second via liner encapsulates a bottom surface and sides of the second through silicon via. 
     
     
         8 . The structure of  claim 7 , further comprising a second conductor wherein the second conductor has a second conductor liner; and wherein the second conductor liner is in direct contact with the second via liner on the bottom surface of the first through silicon via. 
     
     
         9 . The structure of  claim 8 , wherein the first and second conductors are on a same level. 
     
     
         10 . The structure of  claim 8 , further comprising a third conductor electrically connected to the first or second conductor wherein the third conductor is on a different level. 
     
     
         11 . A structure comprising:
 a conductor having a conductor fill material and having a conductor liner covering at least one side of the conductor; and   a via having a via fill material and having a via liner covering at least one side of the via;   wherein the at least one side of the via covered by the via liner is facing and in direct contact with the at least one side of the conductor covered by the wiring liner.   
     
     
         12 . A method of forming an integrated circuit substrate connected to a conductor, the method comprising:
 providing a substrate having a first through silicon via within the substrate wherein the substrate has a backside;   exposing, through the backside of the substrate, an end of the first through silicon via;   forming an insulator over the backside of the substrate and the end of the first through silicon via;   forming an opening in the insulator over the end of the first through silicon via; and   forming a conductor in the opening.   
     
     
         13 . The method of  claim 12 , wherein forming an insulator further comprises forming an etch stop layer adjacent to the backside of the substrate and a dielectric layer adjacent the etch stop layer. 
     
     
         14 . The method of  claim 13 , wherein the etch stop layer is a dielectric layer containing nitrogen. 
     
     
         15 . The method of  claim 13 , wherein the dielectric layer is an oxide layer. 
     
     
         16 . The method of  claim 13 , further comprising planarizing the dielectric layer. 
     
     
         17 . The method of  claim 13 , further comprising providing a second through silicon via;
 wherein the first through silicon via has a first height and the second through silicon via has a second height;   wherein the first and second heights are different.   
     
     
         18 . The method of  claim 13 , wherein forming an opening in the insulator layer includes etching the dielectric layer to the etch stop layer, removing the etch stop layer and exposing a bottom surface of each of the first and second through silicon vias such that the heights of the first and second through silicon vias are different. 
     
     
         19 . The method of  claim 17 , wherein exposing the bottom surface includes removing a via insulator and exposing a via liner; wherein the via liner encapsulates the sides and the bottom surface of the via. 
     
     
         20 . The method of  claim 17 , wherein forming a conductor in the opening further comprises forming a conductor liner in contact with said via liner.