Power semiconductor device

Abstract

A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

1 . A power semiconductor device comprising:
 (a) a semiconductor chip having a first main surface where the source electrode of a power MOSFET is provided and a second main surface;   (b) an active cell region provided substantially in the central part of the first main surface of the semiconductor chip, a chip peripheral region provided in the periphery of the first main surface, and an annular intermediate region provided in the first main surface of the semiconductor chip between the active cell region and the chip peripheral region;   (c) a drift region of a first conductivity type provided in the front surfaces of the active cell region, the chip peripheral region, and the annular intermediate region on the first main surface side of the semiconductor chip;   (d) a first superjunction structure provided in the drift region in substantially the whole of the active cell region;   (e) a second superjunction structure provided in the drift region corresponding to the annular intermediate region; and   (f) a third superjunction structure provided in the drift region corresponding to the chip peripheral region,   wherein at least one of a plurality of column regions of a second conductivity type comprising the second superjunction structure is larger in width than a plurality of column regions of the second conductivity type comprising the first superjunction structure.   
     
     
         2 - 19 . (canceled)