Data processor

Abstract

The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.

1 - 14 . (canceled) 
     
     
         15 . A data processor including a first mode corresponding to a fixed-length instruction, a second mode corresponding to a variable-length instruction set by applying a prefix to the fixed-length instruction, and a third mode corresponding to a non-prefix variable length instruction,
 wherein the fixed-length instruction in the first mode composes a code of a first length, the variable-length instruction in the second mode composes a code of the fixed-length instruction of the first length and a code of the prefix of the first length, the non-prefix variable length instruction in the third mode composes a upper code of the first length and a lower code of the first length,   the data processor comprising:   an instruction fetch unit configured to fetch four codes of a plurality of instructions in parallel and having a plurality of decoders comprising first, second, third, and fourth predecoders, each of which performs predecoding for determining whether a corresponding one of said fetched codes is of a fixed-length instruction in the first mode, a fixed-length instruction corresponding to part of a variable-length instruction in the second mode, a prefix corresponding to part of the variable-length instruction in the second mode, or a upper or lower code corresponding to part of a non-prefix variable length instruction in the third mode;   a first pipeline comprising a first prefix code decode unit and a first fixed-length instruction decode unit, a second pipeline comprising a second prefix code decode unit and a second fixed-length instruction decode unit, a upper variable-length instruction decode unit, and a lower variable-length instruction decode unit;   a first selector for selecting one of outputs of the first, second, third, and fourth predecoders and which outputs the same to the first fixed-length instruction decode unit;   a second selector for selecting one of the outputs of the first, second, third, and fourth predecoders and which outputs the same to the second fixed-length instruction decode unit and the upper variable-length instruction decode unit;   a third selector for selecting one of the outputs of the first, second, third, and fourth predecoders and which outputs the same to the first prefix code decode unit and the lower variable-length instruction decode unit; and   a fourth selector for selecting one of the outputs of the first, second, third, and fourth predecoders and which outputs the same to the second prefix code decode unit,   wherein in the first mode, a first fixed-length instruction is inputted to the first predecoder, a second fixed-length instruction is inputted to the second predecoder, a third fixed-length instruction is inputted to the third predecoder, and a fourth fixed-length instruction is inputted to the fourth predecoder,   wherein the first predecoder predecodes the first fixed-length instruction, the second predecoder predecodes the second fixed-length instruction, the third predecoder predecodes the third fixed-length instruction, and the fourth predecoder predecodes the fourth fixed-length instruction,   wherein the first selector selects one of the outputs of the first through fourth predecoders and outputs the same to the first fixed-length instruction decode unit based on results of determination by the plurality of predecoders,   wherein the second selector selects one of the outputs of the first through fourth predecoders and outputs the same to the second fixed-length instruction decode unit based on results of determination by the plurality of predecoders,   wherein in the second mode, a first prefix corresponding to part of a first variable-length instruction, a third fixed-length instruction corresponding to part of the first variable-length instruction, a second prefix corresponding to part of a second variable-length instruction, or a fourth fixed-length instruction corresponding to part of the second variable-length instruction is inputted to the first predecoder,   wherein the first prefix corresponding to part of the first variable-length instruction, the third fixed-length instruction corresponding to part of the first variable-length instruction, the second prefix corresponding to part of a second variable-length instruction, or the fourth fixed-length instruction corresponding to part of the second variable-length instruction is inputted to the second predecoder,   wherein the first prefix corresponding to part of the first variable-length instruction, the third fixed-length instruction corresponding to part of the first variable-length instruction, the second prefix corresponding to part of a second variable-length instruction, or the fourth fixed-length instruction corresponding to part of the second variable-length instruction is inputted to the third predecoder,   wherein the first prefix corresponding to part of the first variable-length instruction, the third fixed-length instruction corresponding to part of the first variable-length instruction, the second prefix corresponding to part of a second variable-length instruction, or the fourth fixed-length instruction corresponding to part of the second variable-length instruction is inputted to the fourth predecoder,   wherein the first predecoder predecodes the first prefix, the third fixed-length instruction, the second prefix, or the fourth fixed-length instruction,   wherein the second predecoder predecodes the first prefix, the third fixed-length instruction, the second prefix, or the fourth fixed-length instruction,   wherein the third predecoder predecodes the first prefix, the third fixed-length instruction, the second prefix, or the fourth fixed-length instruction,   wherein the fourth predecoder predecodes the first prefix or the third fixed-length instruction or the second prefix or the fourth fixed-length instruction,   wherein the third selector or the fourth selector selects one of the output of the first predecoder, the output of the second predecoder, the output of the third predecoder, or the output of the fourth predecoder, and outputs the same to the first prefix code decode unit or the second prefix code decode unit, based on results of determination by the plurality of predecoders,   wherein the first selector or the second selector selects one of the outputs of the first through fourth predecoders and outputs the same to the first fixed-length instruction decode unit or the second fixed-length instruction decode unit, based on results of determination by the plurality of predecoders,   wherein in the first prefix corresponding to part of the first variable-length instruction is supplied to the first prefix code decode unit, followed by supply of the third fixed-length instruction to the first fixed-length instruction decode unit, and the second prefix corresponding to part of the second variable-length instruction is supplied to the second prefix code decode unit, followed by supply of the fourth fixed-length instruction to the second fixed-length instruction decode unit, based on results of determination by the plurality of predecoders, respectively,   wherein in the third mode, a first upper code corresponding to part of a first non-prefix variable-length instruction, a first lower code corresponding to part of the first non-prefix variable-length instruction, a second upper code corresponding to part of a second non-prefix variable-length instruction, or a second lower code corresponding to part of the second non-prefix variable-length instruction is inputted to the first predecoder,   wherein the first upper code corresponding to part of the first non-prefix variable-length instruction, the first lower code corresponding to part of the first non-prefix variable-length instruction, the second upper code corresponding to part of the second non-prefix variable-length instruction, or the second lower code corresponding to part of the second non-prefix variable-length instruction is inputted to the second predecoder,   wherein the first upper code corresponding to part of the first non-prefix variable-length instruction, the first lower code corresponding to part of the first non-prefix variable-length instruction, the second upper code corresponding to part of the second non-prefix variable-length instruction, or the second lower code corresponding to part of the second non-prefix variable-length instruction is inputted to the third predecoder,   wherein the first upper code corresponding to part of the first non-prefix variable-length instruction, the first lower code corresponding to part of the first non-prefix variable-length instruction, the second upper code corresponding to part of the second non-prefix variable-length instruction, or the second lower code corresponding to part of the second non-prefix variable-length instruction is inputted to the fourth predecoder,   wherein the first predecoder predecodes the upper or the lower code of the first non-prefix variable-length instruction, or the upper or the lower code of the second non-prefix variable-length instruction,   wherein the second predecoder predecodes the upper or the lower code of the first non-prefix variable-length instruction, or the upper or the lower code of the second non-prefix variable-length instruction,   wherein the third predecoder predecodes the upper or the lower code of the first non-prefix variable-length instruction, or the upper or the lower code of the second non-prefix variable-length instruction,   wherein the fourth predecoder predecodes the upper or the lower code of the first non-prefix variable-length instruction, or the upper or the lower code of the second non-prefix variable-length instruction,   wherein the second selector selects one of the output of the first predecoder, the output of the second predecoder, the output of the third predecoder, or the output of the fourth predecoder, and outputs to the upper variable-length instruction decode unit, based on results of determination by the plurality of predecoders, and   wherein the third selector selects one of the output of the first predecoder, the output of the second predecoder, the output of the third predecoder, or the output of the fourth predecoder, and outputs to the lower variable-length instruction decode unit, based on results of determination by the plurality of predecoders.   
     
     
         16 . The data processor according to  claim 15 , wherein in the first mode, the supply of power to the first and second prefix decode units and the upper and lower variable-length instruction decode units is cut off. 
     
     
         17 . The data processor according to  claim 15 , wherein in the second mode, the supply of power to the upper and lower variable-length instruction decode units is cut off. 
     
     
         18 . The data processor according to  claim 15 ,
 wherein each of the first, second, third and fourth predecoders outputs an instruction attribute signal indicative of whether the input instruction is of a fixed-length instruction in the first mode, a fixed-length instruction corresponding to part of a variable-length instruction in the second mode, a prefix corresponding to part of the variable-length instruction in the second mode, or a upper or lower code of the non-prefix variable length instruction in the third mode.   
     
     
         19 . The data processor according to  claim 15 , further comprising mode registers for performing the setting of stopping the operations of the first and second prefix code decode units and the upper and lower variable-length instruction decode units or invalidating the first and second prefix code decode units and the upper and lower variable-length instruction decode units in the first mode. 
     
     
         20 . The data processor according to  claim 15 , further comprising mode registers for performing the setting of stopping the operations of the upper and lower variable-length instruction decode units or invalidating the first and second prefix code decode units and the upper and lower variable-length instruction decode units in the second mode.