Method for managing a memory apparatus

Abstract

A memory apparatus includes at least one NV memory element, which includes a plurality of blocks. A method for managing the memory apparatus includes: receiving a first access command from a host; analyzing the first access command to obtain a first host address; linking the first host address to a first page of the physical block; receiving a second access command from the host; analyzing the second access command to obtain a second host address; linking the second host address to a second page of the physical block; recording a valid/invalid page count of the physical block corresponding to accessing pages of the physical block; and determining whether to erase a portion of the blocks according to the valid/invalid page count. A difference value of the first host address and the second host address is greater than a number of pages of the physical block.

What is claimed is: 
     
         1 . A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks, the method comprising:
 receiving a first access command from a host;   analyzing the first access command to obtain a first host address;   linking the first host address to at least a first page of the physical block;   receiving a second access command from the host;   analyzing the second access command to obtain a second host address;   linking the second host address to at least a second page of the physical block;   recording a valid/invalid page count of at least the physical block corresponding to accessing pages of the physical block; and   determining whether to erase a portion of the blocks according to the valid/invalid page count;   wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block.   
     
     
         2 . The method of  claim 1 , further comprising:
 analyzing the first access command to obtain first data;   analyzing the second access command to obtain second data;   storing the first data into the physical block; and   storing the second data into the physical block.   
     
     
         3 . A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks, the method comprising:
 receiving a first access command from a host;   analyzing the first access command to obtain a first host address;   linking the first host address to at least a page of a first physical block;   receiving a second access command from the host;   analyzing the second access command to obtain a second host address;   linking the second host address to at least a page of a second physical block that is different from the first physical block;   recording a valid/invalid page count of each physical block corresponding to accessing pages of each physical block; and   determining whether to erase a portion of the blocks according to the valid/invalid page count;   wherein a difference value of the first host address and the second host address is smaller than a number of pages of each physical block.   
     
     
         4 . The method of  claim 3 , further comprising:
 analyzing the first access command to obtain first data;   analyzing the second access command to obtain second data;   storing the first data into the first physical block; and   storing the second data into the second physical block.   
     
     
         5 . The method of  claim 4 , wherein the first host address is linked to at least a first page of the first physical block, and the second host address is linked to at least a second page of the second physical block. 
     
     
         6 . A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks, the blocks being logically divided into a data region and a spare region, the method comprising:
 receiving a first access command from a host;   analyzing the first access command to obtain a first host address;   linking the first host address to a physical block belonging to the data region;   receiving a second access command from the host;   analyzing the second access command to obtain a second host address; and   linking the second host address to the physical block;   wherein a difference value of the first host address and the second host address is greater than a number of pages of the physical block.   
     
     
         7 . The method of  claim 6 , further comprising:
 analyzing the first access command to obtain first data;   analyzing the second access command to obtain second data;   storing the first data into at least a first page of the physical block; and   storing the second data into at least a second page of the physical block, wherein the second page of the physical block is next to the first page of the physical block.   
     
     
         8 . The method of  claim 6 , wherein the first host address is linked to at least a first page of the physical block, and the second host address is linked to at least a second page of the physical block. 
     
     
         9 . A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks, the blocks being logically divided into a data region and a spare region, the method comprising:
 receiving a first access command from a host;   analyzing the first access command to obtain a first host address;   linking the first host address to at least a page of a first physical block belonging to the data region;   receiving a second access command from the host;   analyzing the second access command to obtain a second host address; and   linking the second host address to at least a page of a second physical block belonging to the data region, wherein the second physical block is different from the first physical block;   wherein a difference value of the first host address and the second host address is smaller than a number of pages of each physical block.   
     
     
         10 . The method of  claim 9 , further comprising:
 analyzing the first access command to obtain first data;   analyzing the second access command to obtain second data;   storing the first data into the first physical block; and   storing the second data into the second physical block.   
     
     
         11 . The method of  claim 9 , wherein the first host address is linked to at least a first page of the first physical block, and the second host address is linked to at least a second page of the second physical block. 
     
     
         12 . A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks, and a processing unit, the method being performed by the processing unit and comprising:
 providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the at least one local page address linking table comprises linking relationships between a plurality of physical page addresses of the at least one block and a plurality of logical page addresses; and   building a global page address linking table of the memory apparatus according to the at least one local page address linking table.   
     
     
         13 . The method of  claim 12 , wherein the step of providing the block of the memory apparatus with the local page address linking table within the memory apparatus further comprises:
 building a temporary local page address linking table for the local page address linking table corresponding to programming/writing operations of the memory apparatus.   
     
     
         14 . The method of  claim 13 , wherein the local page address linking table is built when at least a data page in the block has been programmed. 
     
     
         15 . The method of  claim 13 , wherein the local page address linking table is built when all data pages in the block has been programmed. 
     
     
         16 . The method of  claim 12 , wherein the local page address linking table is positioned in the block. 
     
     
         17 . The method of  claim 16 , further comprising:
 storing the local page address linking table into a predetermined page of the block.   
     
     
         18 . The method of  claim 12 , wherein the step of providing the block of the memory apparatus with the local page address linking table within the memory apparatus further comprises:
 providing a plurality of blocks of the memory apparatus with a plurality of local page address linking tables within the memory apparatus, respectively;   wherein the step of building the global page address linking table of the memory apparatus according to the local page address linking table further comprises:   building the global page address linking table according to the local page address linking tables.   
     
     
         19 . The method of  claim 18 , wherein the step of building the global page address linking table of the memory apparatus according to the local page address linking table further comprises:
 reading one of the local page address linking tables to update the global page address linking table.   
     
     
         20 . The method of  claim 12 , wherein the step of building the global page address linking table of the memory apparatus according to the local page address linking table further comprises:
 reading each of the local page address linking tables to build the global page address linking table.   
     
     
         21 . The method of  claim 12 , wherein the ranking of a field of the global page address linking table represents a logical page address, and the content of the field represents an associated physical page address. 
     
     
         22 . The method of  claim 12 , wherein a range of the logical page addresses in the local page address linking table is greater than a number of pages in the block. 
     
     
         23 . A memory apparatus, comprising:
 at least one non-volatile (NV) memory element, each of which comprises a plurality of blocks; and   a processing unit arranged to manage the memory apparatus according to a program code embedded in the processing unit or received from outside the processing unit, wherein the processing unit is arranged to provide at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, and the local page address linking table comprises linking relationships between a plurality of physical page addresses of the at least one block and a plurality of logical page addresses;   wherein the processing unit is arranged to build a global page address linking table of the memory apparatus according to the local page address linking table.   
     
     
         24 . The memory apparatus of  claim 23 , wherein the processing unit builds a temporary local page address linking table for the local page address linking table corresponding to programming/writing operations of the memory apparatus. 
     
     
         25 . The memory apparatus of  claim 24 , wherein the local page address linking table is built when at least a data page in the block has been programmed. 
     
     
         26 . The memory apparatus of  claim 24 , wherein the local page address linking table is built when all data pages in the block have been programmed. 
     
     
         27 . The memory apparatus of  claim 23 , wherein the local page address linking table is positioned in the block. 
     
     
         28 . The memory apparatus of  claim 27 , wherein the processing unit stores the local page address linking table into the last page of the block. 
     
     
         29 . The memory apparatus of  claim 23 , wherein the processing unit provides a plurality of blocks of the memory apparatus with a plurality of local page address linking tables within the memory apparatus, respectively; and the processing unit builds the global page address linking table according to the local page address linking tables. 
     
     
         30 . The memory apparatus of  claim 29 , wherein the processing unit reads one of the local page address linking tables to update the global page address linking table. 
     
     
         31 . The memory apparatus of  claim 23 , wherein the processing unit reads each of the local page address linking tables to build the global page address linking table. 
     
     
         32 . The memory apparatus of  claim 23 , wherein the ranking of a field of the global page address linking table represents a logical page address, and the content of the field represents an associated physical page address. 
     
     
         33 . The memory apparatus of  claim 23 , wherein a range of the logical page addresses in the local page address linking table is greater than a number of pages in the block.