Arithmetic circuit and arithmetic apparatus

Abstract

Provided are an arithmetic circuit and an arithmetic apparatus capable of performing comparison involving conditional branch of three or more values at high speed. The arithmetic circuit includes a plurality of computing units, a plurality of selection circuits and a decision unit. The plurality of computing units perform arithmetic computations on input data and output flag information generated based on a result of the computations. The plurality of selection circuits select any one of the data input to the plurality of computing units. The decision unit receives the flag information from the plurality of computing units and controls select operation of each of the plurality of selection circuits.

What is claimed is: 
     
         1 . An arithmetic circuit comprising:
 a plurality of computing units configured to perform arithmetic computations from data inputs and to output a result of computations and a flag information generated based on the result of the computations;   a first selection circuit configured to select and to output maximum value from the data inputs to the plurality of computing units,   a second selection circuit configured to select and to output minimum value from the data inputs to the plurality of computing units,   a third selection circuit configured to output any one of the result of the computations as a difference,   a decision unit configured to receive the flag information from the plurality of computing units and to control select operation of each of the first, second and third selection circuits, and   a register file configured to store data to be used for computations of the plurality of computing units and to receive the outputs of the first, second and third selection circuits.   
     
     
         2 . The arithmetic circuit according to  claim 1 ,
 the plurality of computing units include two terminals which receive data inputs from the register file.   
     
     
         3 . The arithmetic circuit according to  claim 1 ,
 the register file include three terminals which outputs the stored data to be used for computations of the plurality of computing units.