Semiconductor Device Having First and Second Demodulation Circuits For Wireless Communication

Abstract

A device receives ASK signals by using an ASK signal receiving circuit that is different from an ASK signal receiving circuit for R/W mode, when an NFC-enabled semiconductor device operates in a mode other than the R/W mode. An ASK signal receiving circuit for 100% ASK is provided on the side of a pair of transmitting terminals. This arrangement eliminates the influence of an ESD provided within an ASK signal receiving circuit for 10% ASK coupled to a pair of receiving terminals. There is no need for management of threshold values that are different according to type of ASK and it is possible to support different modulation schemes by a smaller circuit configuration.

What is claimed is: 
     
         1 . A semiconductor device for wireless communication, comprising:
 a first demodulation circuit configured to demodulate a first ASK modulated signal;   a second demodulation circuit configured to demodulate a second ASK modulated signal which is modulated at a smaller modulation depth than the first ASK modulated signal;   a driver circuit that outputs a modulated signal;   a protection circuit;   a first pair of external coupling pins coupled to the first demodulation circuit and the driver circuit; and   a second pair of external coupling pins provided separately from the first pair of external coupling pins and coupled to the second demodulation circuit and the protection circuit,   wherein the first pair of external coupling pins receives at least the first ASK modulated signal from an external antenna and transmits the modulated signal to the external antenna,   wherein the second pair of external coupling pins receives at least the second ASK modulated signal from the external antenna.   
     
     
         2 . The semiconductor device for wireless communication according to  claim 1 ,
 wherein the first demodulation circuit is triggered by a level and the second demodulation circuit is triggered by an edge.   
     
     
         3 . The semiconductor device for wireless communication according to  claim 1 , further comprising a circuit for sharing a demodulation logic circuit,
 wherein the circuit for sharing a demodulation logic circuit judges whether the first demodulation circuit or the second demodulation circuit is enabled and selects an output of the enabled receiving circuit as an output to the demodulation logic circuit.   
     
     
         4 . The semiconductor device for wireless communication according to  claim 1 ,
 wherein the second demodulation circuit includes a current drawing circuit and achieves matching by controlling the current drawing circuit.   
     
     
         5 . The semiconductor device for wireless communication according to  claim 1 , wherein the first ASK modulated signal is modulated at a modulation depth of 100%. 
     
     
         6 . The semiconductor device for wireless communication according to  claim 5 , wherein the second ASK modulated signal is modulated at a modulation depth of 10%. 
     
     
         7 . The semiconductor device for wireless communication according to  claim 1 , wherein the protection circuit is configured for clamping so that voltage above a certain level cannot flow in the second demodulation circuit. 
     
     
         8 . The semiconductor device for wireless communication according to  claim 1 , further comprising:
 a resonance circuit connected to the first pair of external coupling pins; and   a resistor divider circuit connected to the second pair of external coupling pins.   
     
     
         9 . The semiconductor device for wireless communication according to  claim 1 , further comprising:
 a circuit for sharing a demodulation logic circuit comprising:
 a first delay circuit receiving an output of the first demodulation circuit and producing a first delay output; 
 a second delay circuit receiving an output of the second demodulation circuit and producing a second delay output; 
 a selected signal reset pulse generating circuit connected to an output of the first demodulation circuit and producing a select output; and 
 a select circuit receiving the first and second delay outputs and the select output, and outputting one of the first and second delay outputs in response to the select output. 
   
     
     
         10 . The semiconductor device for wireless communication according to  claim 9 , wherein:
 in addition to outputting one of the first and second delay outputs in response to the select output, the circuit for sharing a demodulation logic circuit also outputs the select output and a reset output created by the selected signal reset pulse generating circuit.   
     
     
         11 . The semiconductor device for wireless communication according to  claim 1 , comprising:
 a receiving terminal control circuit positioned between the second pair of external coupling pins and the second demodulation circuit, the receiving terminal control circuit comprising:   a current drawing circuit having a plurality of selectively switchable current paths between a common node and ground; wherein:
 at least one selectively switchable current path has a first number of diode-coupled MOSs in series with a resistor; and 
 at least one selectively switchable current path has said first number of diode-coupled MOSs and is devoid of resistors. 
   
     
     
         12 . The semiconductor device for wireless communication according to  claim 1 , comprising:
 a receiving terminal control circuit positioned between the second pair of external coupling pins and the second demodulation circuit, the receiving terminal control circuit comprising:   a current drawing circuit having a plurality of selectively switchable current paths between a common node and ground; wherein:
 a first number of selectively switchable current paths have at least one diode-coupled MOSs in series with resistors of different resistance values; and 
 a second number of selectively switchable current paths are devoid of resistors. 
   
     
     
         13 . The semiconductor device for wireless communication according to  claim 1 , further comprising:
 a receiving terminal control circuit positioned between the second pair of external coupling pins and the second demodulation circuit, the receiving terminal control circuit comprising:   a plurality of resistors, each resistor connected between a common node and ground via a corresponding switch; wherein:
 the common node is connected to a first of the second pair of external coupling pins; and 
 turning on/off a corresponding switch adjusts a resistor divider attenuation associated with the second demodulation circuit.