Semiconductor device

Abstract

The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.

What is claimed is: 
     
         1 . A memory device comprising the:
 a plurality of interconnected memory chips; and   an interface for accessing the plurality of memory chips;   wherein each of the plurality of memory chips includes a boot device recognition signal for programming one of the plurality of memory chips as a boot device.   
     
     
         2 . The memory device as claimed in  claim 1  wherein the boot device stores a boot program. 
     
     
         3 . The memory device as claimed in  claim 1  wherein the boot device is accessed after power-on. 
     
     
         4 . The memory device as claimed in  claim 1  wherein the boot device is a nonvolatile memory chip. 
     
     
         5 . The memory device as claimed in  claim 1  wherein the boot device is a flash memory chip. 
     
     
         6 . The memory device as claimed in  claim 1  wherein the boot device is a NOR flash memory chip. 
     
     
         7 . The memory device as claimed in  claim 1  wherein the boot device recognition signal of a first memory chip among the plurality of memory chips is connected to a first power source to program the first memory chip as the boot device and the boot device recognition signals of memory chips other than the first memory chip among the plurality of memory chips are connected to a second power source. 
     
     
         8 . The memory device as claimed in  claim 7  wherein the first power source is ground and the second power source is Vdd. 
     
     
         9 . The memory device as claimed in  claim 1  wherein the boot device recognition signal is stored as a boot device ID value within each of the plurality of memory chips. 
     
     
         10 . The memory device as claimed in  claim 1  wherein the plurality of memory chips are serially connected. 
     
     
         11 . The memory device as claimed in  claim 1  wherein the interface is a serial interface. 
     
     
         12 . The memory device as claimed in  claim 1  wherein the interface comprises a request interface and a response interface. 
     
     
         13 . The memory device as claimed in  claim 1  wherein the plurality of memory chips are stacked. 
     
     
         14 . The memory device as claimed in  claim 1  wherein the plurality of memory chips are connected by bonding wires. 
     
     
         15 . The memory device as claimed in  claim 1  wherein the plurality of memory chips are integrated in a single sealing body.