Method of forming and structure of a non-volatile memory cell

Abstract

A structure of a memory cell includes a substrate, a well, three source/drain doped regions, two bottom dielectric layers, two charge trapping layers, a blocking layer and two gates to form a storage transistor and a select transistor of the memory cell. A bottom dielectric layer and a charge trapping layer may be used to provide the dielectric of the gate of the select transistor with enough thickness but without any additional fabrication process.

1 . A non-volatile memory cell comprising:
 a well formed on a substrate;   a plurality of source/drain doped regions formed on the well;   a first bottom dielectric layer formed between a first source/drain doped region and a second source/drain doped region of the plurality of source/drain doped regions on the well;   a second bottom dielectric layer formed between the second source/drain doped region and a third source/drain doped region of the plurality of source/drain doped regions on the well;   a first charge trapping layer formed on the first bottom dielectric layer;   a second charge trapping layer formed on the second bottom dielectric layer;   a blocking layer formed on the first charge trapping layer;   a memory gate formed on the blocking layer; and   a select gate formed on the second charge trapping layer.   
     
     
         2 . The non-volatile memory cell in  claim 1 , further comprising:
 a plurality of isolations formed on the substrate to define an active region.   
     
     
         3 . The non-volatile memory cell in  claim 1 , further comprising:
 a plurality of lightly doped regions formed on the well and each formed between a corresponding bottom dielectric layer and a corresponding source/drain doped region.   
     
     
         4 . The non-volatile memory cell in  claim 1 , further comprising:
 a deep well formed between the substrate and the well.   
     
     
         5 . The non-volatile memory cell in  claim 4 , wherein the deep well is a deep N-well. 
     
     
         6 . The non-volatile memory cell in  claim 1 , further comprising:
 a barrier layer formed between the substrate and the well.   
     
     
         7 . The non-volatile memory cell in  claim 6 , wherein the barrier layer is an N-barrier layer. 
     
     
         8 . The non-volatile memory cell in  claim 1 , wherein a length of the select gate is greater than or equal to a length of the memory gate. 
     
     
         9 . The non-volatile memory cell in  claim 1 , wherein the first charge trapping layer and the second charge trapping layer are composed of silicon nitride. 
     
     
         10 . The non-volatile memory cell in  claim 1 , wherein the first charge trapping layer and the second charge trapping layer are composed of silicon oxynitride. 
     
     
         11 . The non-volatile memory cell in  claim 1 , wherein the substrate is a P-substrate, the well is an N-well, and the plurality of source/drain doped regions are P+ doped regions. 
     
     
         12 - 24 . (canceled)