Method of fabricating a non-volatile memory

Abstract

A structure of a memory cell includes a substrate, a well, two source/drain doped regions, a stacked layer and a metal gate. The stacked layer includes a tunneling layer, and a charge trapping layer. A method of fabricating the memory cell may vary with the change in sequence of performing steps. The difference in sequence of fabrication may yield different characteristic variations for the formed components of the memory cell.

What is claimed is: 
     
         1 . A method of forming a memory cell, comprising:
 providing a substrate;   forming a plurality of isolations on the substrate;   forming a well on the substrate;   forming a stacked layer comprising a tunneling layer and a charge trapping layer on the substrate;   forming a high-k gate dielectric layer on the stacked layer;   forming a poly silicon gate on the high-k gate dielectric layer;   forming at least two source/drain doped regions on the well;   removing the poly silicon gate; and   depositing a metal to a removed area of the poly silicon gate to form a metal gate.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a plurality of lightly doped regions on the well;   wherein each of the lightly doped regions is between one of the source/drain doped regions and the stacked layer.   
     
     
         3 . The method of  claim 1 , wherein the stacked layer further comprises a charge stop layer formed on the charge trapping layer. 
     
     
         4 . The method of  claim 3 , wherein the step of forming the well on the substrate is proceeded after the step of forming the stacked layer. 
     
     
         5 . The method of  claim 3 , wherein the step of forming the plurality of isolations is proceeded after the step of forming the stacked layer. 
     
     
         6 . The method of  claim 1 , wherein the step of forming the well on the substrate is proceeded after the step of forming the stacked layer. 
     
     
         7 . The method of  claim 1 , wherein the step of forming the plurality of isolations is proceeded after the step of forming the stacked layer. 
     
     
         8 . A method of forming a memory cell, comprising:
 providing a substrate;   forming a plurality of isolations on the substrate;   forming a well on the substrate;   forming a high-k gate dielectric layer on the well;   forming a poly silicon gate on the high-k gate dielectric layer;   forming at least two source/drain doped regions on the well;   removing the poly silicon gate;   forming a stacked layer comprising a tunneling layer, a charge trapping layer and a charge stop layer on a removed area of the poly silicon gate; and   depositing a metal to the removed area of the poly silicon gate to form a metal gate.   
     
     
         9 . The method of  claim 8 , further comprising:
 forming a plurality of lightly doped regions on the well;   wherein each of the lightly doped regions is between one of the source/drain doped regions and the stacked layer.   
     
     
         10 . A memory cell, comprising:
 isolations formed on a substrate;   a well formed directly on the substrate wherein the isolations define a region of the well;   at least two source/drain doped regions formed on the well;   a stacked layer comprising a tunneling layer and a charge trapping layer formed between the at least two source/drain doped regions on the well;   a high-k gate dielectric layer formed on the stacked layer; and   a metal gate formed on the high-k gate dielectric layer.   
     
     
         11 . The memory cell of  claim 10 , wherein the stacked layer further comprises:
 a charge stop layer formed on the charge trapping layer.   
     
     
         12 . The memory cell of  claim 11 , wherein the charge stop layer is a high-k dielectric layer. 
     
     
         13 . The memory cell of  claim 10 , further comprising:
 a spacer formed on each of at least two sides of the metal gate.   
     
     
         14 . The memory cell of  claim 13 , further comprising interlayer dielectric formed on the substrate encompassing the spacer. 
     
     
         15 . The memory cell of  claim 10 , further comprising:
 lightly doped regions formed on the well;   wherein each of the lightly doped regions is between one of the source/drain doped regions and the stacked layer.   
     
     
         16 . The memory cell of  claim 10 , wherein the tunneling layer is a high-k dielectric layer. 
     
     
         17 . The memory cell of  claim 10 , wherein the metal gate is formed of tungsten, aluminum, titanium nitride, tantalum nitride, tantalum or copper. 
     
     
         18 . The memory cell of  claim 10 , wherein the substrate is a P-substrate, the well is an N-well, and the source/drain doped regions are P-type source/drain doped regions.