Clock signals for dynamic reconfiguration of communication link bundles

Abstract

In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles.

What is claimed is: 
     
         1 . An electronic device, comprising:
 a plurality of communication link bundles that provide communication between a processor of the electronic device and other components of the electronic device, wherein at least one of the communication link bundles comprises a plurality of communication lanes; and   a plurality of clock selection circuits, one for each communication link bundle, each one dynamically selecting a clock signal out of multiple clock signals for use by its respective communication link bundle.   
     
     
         2 . The electronic device of  claim 1 , wherein the plurality of communication link bundles are compatible with a PCI Express communication protocol. 
     
     
         3 . The electronic device of  claim 1 , further comprising a clock distribution hub that receives an input clock and outputs the multiple clock signals. 
     
     
         4 . The electronic device of  claim 3 , wherein the multiple clock signals include a first clock signal that is a buffered version of the input clock and a second clock signal that is a buffered and divided version of the input clock. 
     
     
         5 . The electronic device of  claim 3 , wherein the multiple clock signals each have a different data rate, and wherein the clock distribution hub maintains phase alignment between the multiple clock signals. 
     
     
         6 . The electronic device of  claim 3 , wherein one of the multiple clock signals has a PCI Express Gen 1 data rate and another of the multiple clock signals has a PCI Express Gen 2 data rate. 
     
     
         7 . The electronic device of  claim 1 , wherein a serial communication link controller is capable of dynamically re-bundling the communication link bundles to change the number of communication lanes associated with each communication link bundle. 
     
     
         8 . The electronic device of  claim 7 , wherein a clock distribution hub maintains phase alignment between the multiple clock signals even when the dynamically re-bundling occurs. 
     
     
         9 . The electronic device of  claim 1 , wherein each clock selection circuit includes at least one multiplexer that receives the multiple clock signals and selects the clock signal for its respective communication link bundle. 
     
     
         10 . A serial communication link controller of an electronic device, comprising:
 a plurality of communication link bundles that provide communication between a processor of the electronic device and other components of the electronic device, wherein at least one of the communication link bundles comprises a plurality of communication lanes; and   a plurality of clock selection circuits, at leash one for each communication link bundle, each one dynamically selecting a clock signal out of multiple clock signals for use by at least part of its respective communication link bundle.   
     
     
         11 . The serial communication link controller of  claim 10 , further comprising a clock distribution hub that receives an input clock and outputs the multiple clock signals, wherein the multiple clock signals each have a different data rate, and wherein the clock distribution hub maintains phase alignment between the multiple clock signals. 
     
     
         12 . The serial communication link controller of  claim 11 , wherein the clock distribution hub includes at least one clock divider to provide one of the multiple clock signals with a frequency that is half the frequency of another one of the multiple clock signals. 
     
     
         13 . The serial communication link controller of  claim 10 , wherein at least one of the communication link bundles has multiple clock selection circuits, each one dynamically selecting a clock signal for part of its respective communication link bundle. 
     
     
         14 . A method, comprising:
 providing a plurality of communication link bundles that allow for communication between a processor of an electronic device and other components of the electronic device, wherein at least one of the communication link bundles comprises a plurality of communication lanes;   generating multiple clock signals based on an input clock;   dynamically selecting, by each of a plurality of clock selection circuits, a clock signal out of multiple clock signals, wherein each clock selection circuit is associated with one of the communication link bundles; and   using, by each communication link bundle, the clock signal selected for the particular communication link bundle.   
     
     
         15 . The method of  claim 14 , wherein one of the multiple clock signals has a data rate of 5.0 Gbps and another of the multiple clock signals has a data rate of 2.5 Gbps.