US2015085913A1PendingUtilityA1

Data receiving circuit and semiconductor device

Assignee: LAPIS SEMICONDUCTOR CO LTDPriority: Aug 20, 2012Filed: Dec 4, 2014Published: Mar 26, 2015
Est. expiryAug 20, 2032(~6.1 yrs left)· nominal 20-yr term from priority
H04L 27/01H04L 27/3809H04L 27/066H04L 25/03878H04L 25/0274
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Claims

Abstract

A data receiving circuit that can accurately obtain a data signal corresponding to information data from a high speed high density transmitted signal, and a semiconductor device including the data receiving circuit. The amplitude of a first differential signal corresponding to a level difference between a pair of received differential signals, generated in a first differential stage, is amplified and binalized to obtain a received data signal. A second differential signal corresponding to the level difference between the received differential signals, and a third differential signal which is a phase-inverted signal of the second differential signal are generated in a second differential stage provided separately, and a current corresponding to the second differential signal and a current corresponding to the third differential signal are discharged into the respective ones of the pair of transmission lines, thereby suppressing the amplitudes of the received differential signals.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A data receiving circuit for obtaining a received data signal from a pair of received differential signals received through a pair of transmission lines, said data receiving circuit comprising:
 a differential stage configured to generate a first differential signal corresponding to a level difference between said pair of received differential signals;   a level converting and outputting stage configured to binarize a signal obtained by amplifying an amplitude of said first differential signal to output the binarized signal as said received data signal; and   an equalizer configured to suppress the amplitudes of the received differential signals in a section in which the received differential signals alter slowly.   
     
     
         2 . The data receiving circuit according to  claim 1 , wherein said equalizer discharges a current corresponding to the first differential signal and a current corresponding to a phase-inverted signal of the first differential signal to respective ones of said pair of transmission lines. 
     
     
         3 . A semiconductor device including a data receiving circuit for obtaining a received data signal from a pair of received differential signals received through a pair of transmission lines, said data receiving circuit comprising:
 a differential stage configured to generate a first differential signal corresponding to a level difference between said pair of received differential signals;   a level converting and outputting stage configured to binarize a signal obtained by amplifying an amplitude of said first differential signal to output the binarized signal as said received data signal; and   an equalizer configured to suppress the amplitudes of the received differential signals in a section in which the received differential signals alter slowly.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein said equalizer discharges a current corresponding to the first differential signal and a current corresponding to a phase-inverted signal of the first differential signal to respective ones of said pair of transmission lines.

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