Resistance change memory

Abstract

A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween.

1 . (canceled) 
     
     
         2 . A resistance change memory comprising:
 a first conductive line extending in a first direction;   a second conductive line extending in a second direction which is crossed to the first direction;   a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines; and   a control circuit which is connected to both of the first and second conductive lines,   wherein the control circuit is configured to control a voltage to change a resistance of the memory element between first and second values reversibly,   wherein the rectifying element is a diode including a first metal layer, a first insulating layer, a second insulating layer, a second metal layer,   wherein the first insulating layer, and the second insulating layer are sandwiched between the first metal layer and the second metal layer, and   wherein the first insulating layer is sandwiched between the first metal layer and the second insulating layer.   
     
     
         3 . The memory according to  claim 2 , wherein barrier height of the first insulating layer differs from barrier height of the second insulating layer. 
     
     
         4 . The memory according to  claim 3 , wherein the barrier height of the first insulating layer is higher than that of the second insulating layer. 
     
     
         5 . The memory according to  claim 2 , wherein electron affinity of the first insulating layer differs from electron affinity of the second insulating layer. 
     
     
         6 . The memory according to  claim 2 , wherein the thickness of the diode is set to the range of 10 nm to 30 nm. 
     
     
         7 . The memory according to  claim 2 , wherein the thickness of the first metal layer and second metal layer are set to 10 nm, the sum of thickness of the first insulating layer and the second insulating layer is set to 1 nm. 
     
     
         8 . The memory according to  claim 2 , wherein the sum of thickness of the first insulating layer and the second insulating layer is set to the range of 0.5 nm to 3 nm. 
     
     
         9 . The memory according to  claim 2 , wherein the first insulating layer is made of SiO 2 , and the second insulating layer is made of TiO 2 . 
     
     
         10 . The memory according to  claim 2 , wherein at least one of the first insulating layer or the second insulating layer is one selected from the group of SiO 2 , SiN, Si 3 N 4 , Al 2 O 3 , SiON, HfO 2 , HfSiON, Ta 2 O 5 , TiO 2 , and SrTiO 3 . 
     
     
         11 . The memory according to  claim 2 , wherein at least one of the first insulating layer or the second insulating layer is made of Si-based material such as SiO 2 , SiN, and SiON, each of the oxygen element and nitrogen element has a concentration of 1×10 18  atoms/cm 3  or more. 
     
     
         12 . The memory according to  claim 2 , wherein at least one of the first insulating layer or the second insulating layer includes one of an impurity atom, a semiconductor dot, and a metal dot, which form a defect level. 
     
     
         13 . The memory according to  claim 2 , wherein at least one of the first metal layer or the second metal layer is made of one of A) a single element, B) compound metal that is an oxide, carbide, boride, nitride, or silicide, and C) one or a combination of TiN X , TiC X , TiB X , TiSi x , TaC x , TaB x , TaN x , WC x , WB x , W, WSi x , TaC x , TaB, TaN x , TaSi x , HfSi x , Hf, YSi x , and ErSi x , wherein the suffix x indicates any composition ratio. 
     
     
         14 . The memory according to  claim 2 , wherein the diode further including a third insulating layer, and
 wherein the third insulating layer is sandwiched between the second insulating layer and the second metal layer.   
     
     
         15 . The memory according to  claim 14 , wherein the first insulating layer, the second insulating layer, and the third insulating layer differ have different barrier heights. 
     
     
         16 . The memory according to  claim 14 , wherein the first insulating layer is made of SiO 2 , the second insulating layer is made of TiO 2 , and the third insulating layer is made of SiN. 
     
     
         17 . The memory according to  claim 14 , wherein at least one of the first insulating layer, the second insulating layer or the third insulating layer is one selected from the group of SiO 2 , SiN, Si 3 N 4 , Al 2 O 3 , SiON, HfO 2 , HfSiON, Ta 2 O 5 , TiO 2 , and SrTiO 3 . 
     
     
         18 . The memory according to  claim 14 , wherein at least one of the first insulating layer, the second insulating layer or the third insulating layer is made of Si-based material such as SiO 2 , SiN, and SiON, each of the oxygen element and nitrogen element has a concentration of 1×10 18  atoms/cm 3  or more. 
     
     
         19 . The memory according to  claim 14 , wherein at least one of the first insulating layer, the second insulating layer or the third insulating layer includes one of an impurity atom, a semiconductor dot, and a metal dot, which form a defect level. 
     
     
         20 . The memory according to  claim 14 , wherein at least one of the first metal layer or the second metal layer is made of one of A) a single element, B) compound metal that is an oxide, carbide, boride, nitride, or silicide, and C) one or a combination of TiN x , TiC X , TiB X , TiSi x , TaC x , TaB x , TaN x , WC x , WB x , W, WSi x , TaC x , TaB, TaN x , TaSi x , HfSi x , Hf, YSi x , and ErSi x , wherein the suffix x indicates any composition ratio.