Memory controller with flexible data alignment to clock

Abstract

A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.

What is claimed is: 
     
         1 . A system comprising:
 a plurality of series-connected devices that employs source synchronous clocking; and   a controller configured to communicate with the series-connected devices, the controller including:
 an information detector for detecting number information relating to the number of devices connected in-series; and 
 a clock producer for producing an either edge-aligned or center-aligned clock signal with data in response to detection that a device identifier assignment is completed or in progress, the produced clock signal being used for synchronizing communication between the controller and the devices.