Nonvolatile memory device and method for fabricating the same

Abstract

This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.

1 - 7 . (canceled) 
     
     
         8 . A method for fabricating a nonvolatile memory device, comprising:
 forming a groove by selectively etching a substrate;   forming a conductive layer for a gate electrode, that has at least one or more sacrificial layer patterns over the substrate, so that the groove is filled with the conductive layer; and   forming a pipe connection gate electrode by selectively etching the conductive layer for a gate electrode.   
     
     
         9 . The method of  claim 8 , wherein the groove is formed by etching the substrate under a region where the pipe connection gate electrode is foamed. 
     
     
         10 . The method of  claim 8 , wherein the forming of the conductive layer for a gate electrode comprises:
 forming a first conductive layer for a gate electrode over the substrate in which the groove is formed; and   forming a second conductive layer for a gate electrode that includes the sacrificial layer patterns over the first conductive layer.   
     
     
         11 . The method of  claim 10 , wherein the first conductive layer is formed to a thickness that fully fills the groove. 
     
     
         12 . The method of  claim 10 , further comprising forming a third conductive layer over the second conductive layer and the sacrificial layer patterns, after fanning the second conductive layer. 
     
     
         13 . The method of  claim 8 , wherein the pipe connection gate electrode is formed by separating the conductive layer on a block basis. 
     
     
         14 . The method of  claim 8 , wherein the sacrificial layer patterns comprise a material having an etch rate different from an etch rate of the conductive layer for a gate electrode. 
     
     
         15 . The method of  claim 8 , wherein:
 the substrate comprises a cell region and a peripheral region, and   in the forming of the pipe connection gate electrode, peripheral gate electrodes are formed by selectively etching the conductive layer for a gate electrode in the peripheral region.   
     
     
         16 . The method of  claim 8 , further comprising:
 alternately stacking a plurality of first material layers and a plurality of second material layers over the substrate in which the pipe connection gate electrode is formed, after forming the pipe connection gate electrode;   forming pairs of main channel holes through which the sacrificial layer patterns are exposed by selectively etching the first material layers and the second material layers;   forming pipe channel holes each configured to couple each of the pairs of main channel holes by removing the sacrificial layer patterns; and   forming channel layers in the pairs of main channel holes and the pipe channel holes.   
     
     
         17 . The method of  claim 16 , wherein:
 the first material layers are interlayer insulating layers, and   the second material layers are sacrificial layers.   
     
     
         18 . The method of  claim 16 , further comprising forming a memory layer on inner walls of the pairs of main channel holes and the pipe channel holes, after forming the pipe channel holes. 
     
     
         19 . The method of  claim 16 , wherein the second material layers comprise a material having an etch rate different from an etch rate of the first material layers. 
     
     
         20 . The method of  claim 16 , further comprising:
 forming slits to a depth that penetrates the plurality of second material layers on both sides of the main channel hole, after forming the channel layer;   removing the second material layers exposed by the slits; and   forming cell gate electrodes in spaces where the second material layers are removed.