3-d nonvolatile memory device and method of manufacturing the same

Abstract

A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.

What is claimed is: 
     
         1 . A method of manufacturing a three-dimensional (3-D) nonvolatile memory device, the method comprising:
 forming a support protruded from a surface of a substrate and configured to have an inclined sidewall;   forming channel structures each configured to comprise first interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the etched face of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; and   forming select lines coupled to the respective channel layers at the contact region.   
     
     
         2 . The method of  claim 1 , wherein forming the support comprises forming the support by etching the substrate. 
     
     
         3 . The method of  claim 1 , wherein forming the support comprises:
 forming an insulating layer on the substrate; and   forming the support by etching the insulating layer.   
     
     
         4 . The method of  claim 1 , wherein forming the support comprises:
 forming a dummy structure on the substrate; and   forming an insulating layer on an entire surface of the substrate on which the dummy structure is formed.   
     
     
         5 . The method of  claim 1 , wherein forming the supports comprises:
 forming a transistor in a peripheral circuit region and a dummy transistor in a region of the support; and   forming an insulating layer on an entire surface of the substrate in which the dummy transistor is formed.   
     
     
         6 . The method of  claim 1 , wherein forming the channel structures comprises:
 alternately forming the first interlayer insulating layers and the channel layers over an entire surface of the substrate including the support;   performing a planarizing process on the first interlayer insulating layers and the channel layers until a surface of the support is exposed; and   forming the channel structures by patterning the first interlayer insulating layers and the channel layers before or after performing the planarizing process.   
     
     
         7 . The method of  claim 1 , wherein forming the select lines comprises:
 forming a second interlayer insulating layer on the substrate on which the channel structures are formed;   forming the select lines on the second interlayer insulating layer;   forming contact holes through which the respective channel layers are exposed by etching the plurality of select lines and the second interlayer insulating layer;   forming a gate insulating layer on inner walls of the plurality of contact holes; and   forming a pillar type channel layer within the contact holes on which the gate insulating layer is formed.   
     
     
         8 . The method of  claim 7 , further comprising forming bit lines coupled to the pillar type channels and extended in a direction identical with the channel structures, after forming the select lines. 
     
     
         9 . The method of  claim 1 , wherein forming the select lines comprises:
 forming a first interlayer insulating layer on the substrate on which the channel structures are formed;   forming first select lines on the first interlayer insulating layer, wherein the first select lines are placed over some of the plurality of channel layers;   forming a second interlayer insulating layer on the first interlayer insulating layer on which the first select lines are formed;   forming second select lines on the second interlayer insulating layer, wherein the second select lines are placed over remaining channel layers of the plurality of channel layers;   forming a third interlayer insulating layer on the second interlayer insulating layer on which the second select lines are formed;   forming contact holes through which the respective channel layers are exposed by etching the third interlayer insulating layer, the second select lines, the second interlayer insulating layer, the first select lines, and the first interlayer insulating layer;   forming a gate insulating layer on inner walls of the contact holes; and   forming a pillar type channel layer within the contact holes on which the gate insulating layer is formed.   
     
     
         10 . The method of  claim 1 , wherein forming the select lines comprises:
 forming a first interlayer insulating layer on the substrate on which the channel structures are formed;   forming first select lines on the first interlayer insulating layer, wherein each of the first select lines are placed over at least two channel layers adjacent to each other, from among the plurality of channel layers;   forming a second interlayer insulating layer on the first interlayer insulating layer on which the first select lines are formed;   forming second select lines on the second interlayer insulating layer, wherein each of the second select lines are placed over at least two channel layers adjacent to each other, from among the second interlayer insulating layer, so that the second select lines and the first select lines are arranged in a staggered type, and the second select lines and the first select lines adjacent to each other in the stack direction are coupled to the same channel layer;   forming a third interlayer insulating layer on the second interlayer insulating layer on which the second select lines are formed;   forming contact holes through which the respective channel layers are exposed by etching the third interlayer insulating layer, the second select lines, the second interlayer insulating layer, the first select lines, and the first interlayer insulating layer;   forming a gate insulating layer on inner walls of the contact holes; and   forming a pillar type channel layer within the contact holes on which the gate insulating layer is formed.