Semiconductor memory device and driving method of semiconductor memory device

Abstract

A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m.

1 . (canceled) 
     
     
         2 . A semiconductor memory device comprising:
 a writing bit line;   a writing word line;   a reading bit line;   a reading word line;   a memory cell;   an inverting amplifier circuit configured to supply an inverted and amplified potential of the reading bit line to the writing bit line; and   a switch provided between the reading bit line and an input terminal of the inverting amplifier circuit,   wherein the memory cell comprises a writing transistor, a reading transistor, and a capacitor comprising a first electrode and a second electrode,   wherein the switch is configured to control the connection between the reading bit line and the input terminal of the inverting amplifier circuit, depending on whether the memory cell is rewritten with new data or not,   wherein one of a source and a drain of the writing transistor, a gate of the reading transistor, and the first electrode of the capacitor are connected to each other,   wherein the other of the source and the drain of the writing transistor is connected to the writing bit line,   wherein a gate of the writing transistor is connected to the writing word line,   wherein one of a source and a drain of the reading transistor is connected to the reading bit line, and   wherein the second electrode of the capacitor is connected to the reading word line.   
     
     
         3 . The semiconductor memory device according to  claim 2 , wherein the writing transistor and the reading transistor are provided in different layers. 
     
     
         4 . The semiconductor memory device according to  claim 2 , wherein a kind of semiconductor used in the writing transistor and a kind of semiconductor used in the reading transistor are different from each other. 
     
     
         5 . The semiconductor memory device according to  claim 2 , wherein the inverting amplifier circuit is a flip-flop circuit. 
     
     
         6 . The semiconductor memory device according to  claim 2 , wherein the inverting amplifier circuit is an inverter. 
     
     
         7 . A driving method of the semiconductor memory device according to  claim 2 , comprising:
 pre-charging the other of the source and the drain of the writing transistor and the other of the source and the drain of the reading transistor to different potentials;   changing a potential of the reading word line; and   outputting a potential whose phase is opposite to a phase of a potential of the other of the source and the drain of the reading transistor to the other of the source and the drain of the writing transistor with the inverting amplifier circuit.   
     
     
         8 . A semiconductor memory device comprising:
 a writing bit line;   a writing word line;   a reading bit line;   a memory cell;   an inverting amplifier circuit configured to supply an inverted and amplified potential of the reading bit line to the writing bit line,   a switch provided between the reading bit line and an input terminal of the inverting amplifier circuit;   wherein the memory cell comprises a writing transistor and a reading transistor,   wherein the switch is configured to control the connection between the reading bit line and the input terminal of the inverting amplifier circuit, depending on whether the memory cell is rewritten with new data or not,   wherein one of a source and a drain of the writing transistor and a gate of the reading transistor are connected to each other,   wherein the other of the source and the drain of the writing transistor is connected to the writing bit line,   wherein a gate of the writing transistor is connected to the writing word line,   wherein one of a source and a drain of the reading transistor is connected to the reading bit line.   
     
     
         9 . The semiconductor memory device according to  claim 8 , wherein the writing transistor and the reading transistor are provided in different layers. 
     
     
         10 . The semiconductor memory device according to  claim 8 , wherein a kind of semiconductor used in the writing transistor and a kind of semiconductor used in the reading transistor are different from each other. 
     
     
         11 . The semiconductor memory device according to  claim 8 , wherein the inverting amplifier circuit is a flip-flop circuit. 
     
     
         12 . The semiconductor memory device according to  claim 8 , wherein the inverting amplifier circuit is an inverter. 
     
     
         13 . A driving method of the semiconductor memory device according to  claim 8 , comprising:
 pre-charging the reading bit line and the write line to different potentials;   turning on the switch after the pre-charging; and   outputting a potential whose phase is opposite to a phase of a potential of the reading bit line to the write bit line with the inverting amplifier circuit after the turning on the switch.