Microelectronic element with bond elements to encapsulation surface

Abstract

A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.

1 . A microelectronic structure, comprising:
 a semiconductor die having first and second oppositely facing surfaces and a plurality of electrically conductive elements at the first surface;   wire bonds having bases joined to respective ones of the conductive elements, the wire bonds further having free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces thereon, the wire bonds defining edge surfaces extending between the bases and end surfaces thereof; and   a compliant material layer overlying and extending from the first surface of the semiconductor die outside of the bases of the wire bonds, the compliant material layer further extending along first portions of the edge surfaces of the wire bonds at least adjacent the bases thereof and filling spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer, the compliant material layer further having a third surface facing away from the first surface of the semiconductor die, wherein second portions of the wire bonds extend away from the third surface, the second portions including the free ends of the wire bonds.   
     
     
         2 . The microelectronic structure of  claim 1 , wherein the first portions of the wire bonds are encapsulated entirely by the compliant material, and wherein the second portions of the wire bonds are moveable with respect to the bases thereof. 
     
     
         3 . The microelectronic structure of  claim 1 , wherein the compliant material layer has a Young's modulus of 2.5 GPa or less. 
     
     
         4 . The microelectronic structure of  claim 1 , wherein the second portions of the wire bonds extend along axes of the wire bonds that are disposed at angles of at least 30 degrees with respect to the third surface. 
     
     
         5 . The microelectronic structure of  claim 1 , wherein the end surfaces of the wire bonds are positioned above the third surface by a distance of at least 50 microns. 
     
     
         6 . The microelectronic structure of  claim 1 , wherein the semiconductor die further defines edge surfaces extending between the first and second surfaces, and wherein the compliant material layer further includes edge surfaces extending from the third surface thereof to the first surface of the semiconductor die so as to be substantially coplanar with the edge surfaces of the semiconductor die. 
     
     
         7 . The microelectronic structure of  claim 1 , wherein at least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane, a bent portion of the at least one wire bond extending away from the axis within the plane. 
     
     
         8 . The microelectronic structure of  claim 7 , wherein the shape of the at least one wire bond is further such that a substantially straight portion of the wire bond extends between the free end and the bent portion along the axis. 
     
     
         9 . The microelectronic structure of  claim 1 , further including conductive metal masses joined with the second portions of the wire bonds and contacting the third surface of the compliant material layer. 
     
     
         10 . The microelectronic structure of  claim 9 , wherein at least one of the conductive metal masses encapsulates at least some of the second portion of a respective one of the wire bonds. 
     
     
         11 . The microelectronic structure of  claim 9 , wherein the conductive metal masses are configured to join the second portions of the wire bonds with external conductive features by reflow thereof. 
     
     
         12 . The microelectronic structure of  claim 1 , wherein:
 the semiconductor die is a first semiconductor die having a first region and a second region surrounding the first region;   the electrically conductive elements of the first semiconductor die are within the second region;   the microelectronic structure further includes a second semiconductor die mounted on the first semiconductor die within the first region, the second semiconductor die being electrically connected with at least some of the conductive elements of the first semiconductor die; and   the compliant material layer covers the second semiconductor die.   
     
     
         13 . The microelectronic structure of  claim 1 , wherein:
 the semiconductor die is a first semiconductor die having a first region and a second region surrounding the first region;   the electrically conductive elements of the first semiconductor die are within the second region;   the microelectronic structure further includes a second semiconductor die mounted on the first semiconductor die within the first region, the second semiconductor die having first and second oppositely facing surfaces and a plurality of electrically conductive elements at the first surface facing away from the first surface of the first semiconductor die, and wherein additional wire bonds have bases joined to respective ones of the conductive elements of the second semiconductor die, the additional wire bonds further having free ends remote from the bases, the free ends being remote from the first surface of the second semiconductor die and the bases and including the end surfaces thereon, the wire bonds defining edge surfaces extending between the bases and end surfaces thereof; and   the compliant material layer further overlies and extends from the first surface of the second semiconductor die outside of the bases of the additional wire bonds, the compliant material layer further extending along first portions of the edge surfaces of the additional wire bonds, wherein second portions of the additional wire bonds are defined by the end surfaces and portions of the edge surfaces extending from the end surfaces that are uncovered by and extend away from the compliant material layer at the third surface.   
     
     
         14 . A microelectronic package, comprising:
 a microelectronic element, including
 a first semiconductor die having first and second oppositely facing surfaces and a plurality of electrically conductive elements at the first surface; 
 wire bonds having bases joined to respective ones of the conductive elements at the first surface and end surfaces, the end surfaces being remote from the substrate and the bases, each of the wire bonds extending from the base to the end surface thereof; and 
 a compliant material layer overlying and extending from the first portion of the first surface of the substrate and filling spaces between first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer, the compliant material layer having a third surface facing away from the first surface of the substrate, wherein second portions of the wire bonds extend away from the third surface, the second portions including the free ends of the wire bonds; and 
   a substrate having a fourth surface and a plurality of terminals exposed at the fourth surface;   wherein the microelectronic element is mounted on the substrate with the third surface facing the fourth surface and at least some of the wire bonds are joined, at the second portions thereof, to respective ones of the terminals.   
     
     
         15 . The microelectronic package of  claim 14 , wherein the second portions of the wire bonds are electrically and mechanically joined to the terminals by conductive metal masses. 
     
     
         16 . The microelectronic package of  claim 14 , further including a molded dielectric layer formed over at least a portion of the fourth surface of the substrate and extending away therefrom so as to extend along at least a portion of the microelectronic element. 
     
     
         17 . The microelectronic package of  claim 16 , wherein the Young's modulus of the molded dielectric layer is greater than the Young's Modulus of the compliant material layer. 
     
     
         18 . The microelectronic package of  claim 14 , wherein the compliant material layer has a Young's modulus of less than 2.5 GPa. 
     
     
         19 . The microelectronic package of  claim 14 , wherein the wire bonds further define edge surfaces extending between the bases and end surfaces thereof, and wherein the compliant material layer extends along portions of the edge surfaces of the wire bonds at least adjacent the bases thereof and within the first portions of the wire bonds. 
     
     
         20 . The microelectronic package of  claim 19 , wherein portions of the edge surfaces of the wire bonds that extend from the end surfaces thereof are uncovered by the compliant material layer around entire circumferences thereof at the third surface thereof. 
     
     
         21 . A method for making a microelectronic structure, comprising:
 forming wire bonds on a semiconductor die, the semiconductor die having first and second oppositely facing surfaces and a plurality of electrically conductive elements at the first surface, the wire bonds being formed having bases joined to respective ones of the conductive elements and having end surfaces remote from the substrate and the bases, edge surfaces of the wire bonds extending between the bases and the end surfaces; and   forming a compliant material layer overlying and extending from the first surface of the semiconductor die outside of the bases of the wire bonds, the compliant material further being formed to extend along portions of the edge surfaces of first portions of the wire bonds to fill spaces between the first portions of the wire bonds and to separate the first portions of the wire bonds from one another, wherein the compliant material layer is further formed to have a third surface facing away from the first surface of the substrate with second portions of the wire bonds extending away from the third surface, the second portions including the free ends of the wire bonds.