Methods of forming patterns of a semiconductor device

Abstract

Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

What is claimed is: 
     
         1 . A fin-type field effect transistor (FinFET) semiconductor device comprising:
 a first semiconductor pattern extending in a first direction;   a second semiconductor pattern extending in the first direction, and spaced apart from the first semiconductor pattern in a second direction that intersects the first direction; and   a gate on the first and second semiconductor patterns,   wherein a first width of the first semiconductor pattern in the second direction is wider than a second width of the second semiconductor pattern in the second direction.   
     
     
         2 . The device of  claim 1 , wherein:
 a portion of the first semiconductor pattern comprises a first channel region, and   a portion of the second semiconductor pattern comprises a second channel region.   
     
     
         3 . The device of  claim 2 , wherein a first line width of the first channel region is wider than a second line width of the second channel region. 
     
     
         4 . The device of  claim 1 , wherein:
 the first semiconductor pattern comprises a first fin pattern and a second fin pattern spaced apart from each other in the second direction, and   the second semiconductor pattern comprises a third fin pattern and a fourth fin pattern spaced apart from each other in the second direction.   
     
     
         5 . The device of  claim 4 , wherein:
 the first and second fin patterns are spaced apart from each other by a first pitch in the second direction,   the third and fourth fin patterns are spaced apart from each other by a second pitch in the second direction, and   the first pitch and the second pitch are substantially equal.   
     
     
         6 . The device of  claim 1 , wherein the first and second semiconductor patterns protrude from a semiconductor substrate. 
     
     
         7 . The device of  claim 1 , wherein the FinFET semiconductor device has a plurality of threshold voltages. 
     
     
         8 . The device of  claim 1 , wherein the first and second semiconductor patterns share the gate. 
     
     
         9 . A semiconductor device comprising:
 a plurality of first semiconductor patterns extending in a first direction;   a plurality of second semiconductor patterns extending in the first direction, and spaced apart from the first semiconductor patterns in a second direction, the second direction intersecting the first direction; and   a gate on the first and second semiconductor patterns,   wherein a first width of the first semiconductor patterns in the second direction is wider than a second width of the second semiconductor patterns in the second direction.   
     
     
         10 . The semiconductor device of  claim 9 , wherein:
 the semiconductor device comprises a fin-type field effect transistor (FinFET),   a portion of the first semiconductor patterns comprises a first channel region, and   a portion of the second semiconductor patterns comprises a second channel region.   
     
     
         11 . The semiconductor device of  claim 10 , wherein a first line width of the first channel region is wider than a second line width of the second channel region. 
     
     
         12 . The semiconductor device of  claim 9 , wherein:
 the first semiconductor patterns are spaced apart from each other in the second direction, and   the second semiconductor patterns are spaced apart from each other in the second direction.   
     
     
         13 . The semiconductor device of  claim 12 , wherein a first pitch of adjacent portions of the first semiconductor patterns is substantially equal to a second pitch of adjacent portions of the second semiconductor pattern. 
     
     
         14 . A fin-type field effect transistor (FinFET) semiconductor device comprising:
 a semiconductor substrate comprising first and second fin patterns extending in parallel in a first direction, the first and second fin patterns being spaced apart from each other in a second direction that intersects the first direction; and   a gate that is on the semiconductor substrate and is shared by the first and second fin patterns,   wherein a first width of the first fin pattern in the second direction is different from a second width of the second fin pattern in the second direction.   
     
     
         15 . The device of  claim 14 , wherein the first and second fin patterns each comprise two or more spaced-apart portions. 
     
     
         16 . The device of  claim 15 , wherein a first pitch of adjacent ones of the two or more spaced-apart portions of the first fin pattern is substantially equal to a second pitch of adjacent ones of the two or more spaced-apart portions of the second fin pattern. 
     
     
         17 . The device of  claim 14 , wherein the FinFET semiconductor device has a plurality of threshold voltages. 
     
     
         18 . The device of  claim 14 , wherein the semiconductor substrate comprises silicon. 
     
     
         19 . The device of  claim 14 , wherein the first and second fin patterns have a tolerance of about 1 nanometer or less. 
     
     
         20 . A fin-type field effect transistor (FinFET) semiconductor device comprising:
 a plurality of first semiconductor patterns spaced apart from each other by a first pitch;   a plurality of second semiconductor patterns spaced apart from each other by a second pitch; and   a gate on the first and second semiconductor patterns,   wherein a first width of each of the first semiconductor patterns is wider than a second width of each of the second semiconductor patterns, and   wherein the first pitch and the second pitch are substantially equal.