Reducing latency associated with timestamps

Abstract

A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a processor configured to process a plurality of threads, the processor including:
 a plurality of network interfaces for network communication, and 
 a plurality of cores configured to: generate at least one packet including a timestamp for synchronization of the network communication with the network interfaces using a single register write so as to reduce a latency associated with the timestamp, and communicate the packet to at least one of the plurality of network interfaces. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the latency includes memory latency. 
     
     
         3 . The apparatus of  claim 1 , wherein the latency includes interrupt latency. 
     
     
         4 . The apparatus of  claim 3 , wherein the interrupt latency is eliminated by avoiding use of interrupts. 
     
     
         5 . The apparatus of  claim 1 , wherein the at least one of the plurality of cores is coupled to a network for communicating the timestamp. 
     
     
         6 . The apparatus of  claim 1 , wherein the processor includes a timer circuit configured to utilize a time-transfer protocol defined by IEEE 1588. 
     
     
         7 . The apparatus of  claim 1 , wherein the processor includes a programmable timer circuit. 
     
     
         8 . The apparatus of  claim 1 , wherein the processor includes a timer circuit coupled to a plurality of clock frequency sources. 
     
     
         9 . The apparatus of  claim 1 , wherein the processor includes a timer circuit and wherein the timer circuit includes a divider, a multiplier, and an offset sub-circuit. 
     
     
         10 . The apparatus of  claim 1 , wherein the processor includes a timer circuit configured to synchronize the network communication across each of the plurality of network interfaces. 
     
     
         11 . The apparatus of  claim 1 , wherein the packet is a precision time protocol packet. 
     
     
         12 . The apparatus of  claim 1 , wherein the packet including the timestamp is configured to be processed by any selected one of the cores. 
     
     
         13 . The apparatus of  claim 2 , wherein the apparatus is configured to reduce the memory latency by communicating a second timestamp directly from the at least one of the plurality of cores to the at least one of the plurality of network interfaces. 
     
     
         14 . A method of operating a processor including a plurality of cores and a plurality of network interfaces, comprising:
 generating a packet including a timestamp using a single register write to reduce a latency associated with timestamps used for synchronization of network communication; and   communicating the packet to at least one of the plurality of network interfaces.   
     
     
         15 . The method of  claim 14 , wherein the latency includes memory latency. 
     
     
         16 . The method of  claim 14 , wherein the latency includes interrupt latency. 
     
     
         17 . The method of  claim 16 , further comprising avoiding use of interrupts to eliminate interrupt latency. 
     
     
         18 . The method of  claim 14 , further comprising coupling at least one of the plurality of cores to a network for communicating the timestamps. 
     
     
         19 . The method of  claim 14 , further comprising synchronizing the network communication across each of the plurality of network interfaces using a timer circuit. 
     
     
         20 . The method of  claim 15 , further comprising communicating a second timestamp directly from the at least one of the plurality of cores to at least one of the plurality of network interfaces to reduce the memory latency.