Semiconductor Device Having Level Shift Circuit

Abstract

A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 an input node for receiving an input signal;   a first signal path comprising a first plurality of inverters receiving the input signal and outputting a first output signal; and   a second signal path comprising a second plurality of inverters receiving the input signal and outputting a second output signal;   wherein at least one inverter of the second plurality of inverters is powered by one of the first plurality of inverters.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , wherein the input signal is a clock signal. 
     
     
         3 . The semiconductor device as claimed in  claim 1 , wherein the first signal path comprises an odd number of inverters, with the first output signal being an inverted version of the input signal, and the second signal path comprises an even number of inverters, with the second output signal being a non-inverted version of the input signal. 
     
     
         4 . The semiconductor device as claimed in  claim 1 , wherein the first output signal and the second output signal are out-of-phase with respect to each other. 
     
     
         5 . The semiconductor device as claimed in  claim 3 , wherein the first signal path comprises three inverters and the second signal path comprises two inverters. 
     
     
         6 . The semiconductor device as claimed in  claim 5 , wherein the three inverters in the first signal path include a first inverter, a second inverter, and a third inverter connected in series, with the first inverter receiving the input signal, the second inverter receiving an output of the first inverter, and the third inverter receiving an output of the second inverter and outputting the first output signal; and
 wherein the two inverters of the second signal path include a fourth inverter and a fifth inverter connected in series, with the fourth inverter receiving the input signal, and the fifth inverter receiving an output of the fourth inverter and outputting the second output signal.   
     
     
         7 . The semiconductor device as claimed in  claim 6 , wherein each of the first, second, third, fourth, and fifth inverters comprise at least one NMOS transistor and at least one PMOS transistor. 
     
     
         8 . The semiconductor device as claimed in  claim 7 , wherein the NMOS transistors of the first, second, and fourth inverters have substantially the same channel width and the PMOS transistors of the first, second, and fourth inverters have substantially the same channel width. 
     
     
         9 . The semiconductor device as claimed in  claim 7 , wherein the NMOS transistors of the third and fifth inverters have channel widths that differ from the channel width of the NMOS transistors of the first, second, and fourth inverters and the PMOS transistors of the third and fifth inverters have channel widths that differ from the channel width of the PMOS transistors of the first, second, and fourth inverters. 
     
     
         10 . The semiconductor device as claimed in  claim 7 , wherein the NMOS transistors of the first, second and fourth inverters have substantially the same ON resistance and the PMOS transistors of the first, second, and fourth inverters have substantially the same ON resistance. 
     
     
         11 . The semiconductor device as claimed in  claim 6 , wherein the fourth inverter is the at least one inverter of the second plurality of inverters powered by one of the first plurality of inverters, and the first inverter is the one of the first plurality of inverters that powers the fourth inverter. 
     
     
         12 . The semiconductor device as claimed in  claim 11 , wherein the output of the fourth inverter and the output of the second inverter transition state at substantially simultaneous times. 
     
     
         13 . The semiconductor device as claimed in  claim 1 , wherein the number of inverters in the first plurality is one more than the number of inverters in the second plurality. 
     
     
         14 . The semiconductor device as claimed in  claim 1 , wherein the first inverter in the first signal path powers the first inverter in the second signal path. 
     
     
         15 . The semiconductor device as claimed in  claim 1 , comprising:
 a first power supply line that supplies a first voltage; and   a second power supply line that supplies a second voltage lower than the first voltage;   wherein all of the inverters of the first and second pluralities of inverters, except for the at least one inverter of the second plurality of inverters that is powered by one of the first plurality of inverters, is powered using the first and second voltages.   
     
     
         16 . A method comprising:
 receiving an input signal;   providing the input signal to a first signal path comprising a first plurality of inverters;   providing the input signal to a second signal path comprising a second plurality of inverters;   powering at least one inverter of the second plurality of inverters using one of the first plurality of inverters;   outputting a first output signal from the first signal path; and   outputting a second output signal from the second signal path.   
     
     
         17 . The method as claimed in  claim 16 , wherein the number of inverters in first plurality differs from the number of inverters in the second plurality by one. 
     
     
         18 . The method as claimed in  claim 16 , wherein the first plurality of inverters comprises an odd number of inverters and the second plurality of inverters comprises an even number of inverters and the first output signal and the second output signal are inverted with respect to each other. 
     
     
         19 . The method as claimed in  claim 16 , wherein the first plurality of inverters includes a first inverter that receives the input signal and the second plurality of inverters includes a second inverter that receives the input signal, and wherein powering at least one of the inverters of the second plurality comprises powering the second inverter using an output of the first inverter. 
     
     
         20 . The method as claimed in  claim 16 , comprising:
 providing a first voltage from a first power supply line;   providing a second voltage from a second power supply line, the second voltage being lower than the first voltage; and   using the first and second voltages to power each of the inverters of the first and second pluralities of inverters except for the at least one inverter of the second plurality of inverters that is powered by one of the first plurality of inverters.