Solid-state imaging device and manufacturing method thereof

Abstract

According to one embodiment, a solid-state imaging device includes a photodiode includes an N-type region and a P-type region, a floating diffusion region, and a transfer transistor. The N-type diffusion region of the photodiode comprises a first semiconductor region and a second semiconductor region formed shallower than the first semiconductor region. An end portion of the first semiconductor region is positioned on the floating diffusion region side rather than an end portion of a gate electrode of the transfer transistor. An end portion of the second semiconductor region is set in substantially the same position as that of the end portion of the gate electrode of the transfer transistor.

What is claimed is: 
     
         1 . A solid-state imaging device comprising:
 a semiconductor substrate;   a photodiode provided in the semiconductor substrate and comprising an N-type region and a P-type region;   a floating diffusion region provided in the semiconductor substrate to hold charges transferred from the photodiode; and   a transfer transistor provided on the semiconductor substrate to transfer charges stored in the photodiode to the floating diffusion region,   wherein the N-type diffusion region of the photodiode comprises a first semiconductor region and a second semiconductor region formed shallower than the first semiconductor region,   an end portion of the first semiconductor region is positioned on the floating diffusion region side rather than an end portion of a gate electrode of the transfer transistor, and   an end portion of the second semiconductor region is set in substantially the same position as that of the end portion of the gate electrode of the transfer transistor.   
     
     
         2 . The device of  claim 1 , wherein an end portion of the P-type region of the photodiode is set in substantially the same position as that of the end portion of the gate electrode of the transfer transistor. 
     
     
         3 . The device of  claim 1 , wherein a depth of peak impurity concentration of the second semiconductor region is shallower than a depth of peak impurity concentration of the first semiconductor region. 
     
     
         4 . The device of  claim 1 , wherein a depth of peak impurity concentration of the P-type region is shallower than a depth of peak impurity concentration of the second semiconductor region. 
     
     
         5 . The device of  claim 1 , wherein the second semiconductor region is formed in a self-alignment with the gate electrode of the transfer transistor used as a mask. 
     
     
         6 . The device of  claim 1 , wherein the P-type region is formed in a self-alignment with the gate electrode of the transfer transistor used as a mask. 
     
     
         7 . A manufacturing method of a solid-state imaging device that includes a photodiode and a transfer transistor configured to transfer charges stored in the photodiode to a floating diffusion region, the method comprising:
 doping N-type impurities into a semiconductor substrate to form a first semiconductor region of the photodiode in the semiconductor substrate;   forming a gate electrode of the transfer transistor on the semiconductor substrate; and   doping N-type impurities into the semiconductor substrate with the gate electrode used as a mask to form a second semiconductor region of the photodiode at a position shallower than the first semiconductor region in the semiconductor substrate.   
     
     
         8 . The method of  claim 7 , wherein an acceleration energy of impurities used when the second semiconductor region is formed is lower than an acceleration energy of impurities used when the first semiconductor region is formed. 
     
     
         9 . The method of  claim 7 , further comprising doping P-type impurities into the semiconductor substrate with the gate electrode used as a mask to form a third semiconductor region of the photodiode at a position shallower than the second semiconductor region in the semiconductor substrate. 
     
     
         10 . The method of  claim 7 , further comprising forming a mask layer on the semiconductor substrate,
 wherein the first semiconductor region is formed by use of the mask layer.   
     
     
         11 . The method of  claim 7 , wherein the second semiconductor region is formed in a self-alignment with the gate electrode of the transfer transistor used as a mask. 
     
     
         12 . The method of  claim 9 , wherein the third semiconductor region is formed in a self-alignment with the gate electrode of the transfer transistor used as a mask.