US2015067277A1PendingUtilityA1

Multiprocessor system for restricting an access request to a shared resource

Assignee: RENESAS ELECTRONICS CORPPriority: Mar 26, 2007Filed: Nov 5, 2014Published: Mar 5, 2015
Est. expiryMar 26, 2027(~0.7 yrs left)· nominal 20-yr term from priority
Inventors:Masayuki Daito
G06F 9/468G06F 2212/1008G06F 12/1441G06F 21/78
51
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Claims

Abstract

A multiprocessor system including a first processor element, and a second processor element that includes a CPU, a shared resource unit shared by the first and second processor elements, a protection setting unit and a guard unit, and the protection setting unit sets an access protection range for the shared resource unit, the guard unit restricts an access request from the first processor element to the shared resource unit based on the access protection range, the guard unit issues an exceptional access notification signal when the access request from the first processor element is within the access protection range, and when the exceptional access notification signal is issued, the CPU extends the access protection range in such a manner that the extended access protection range is wider than the access protection range set before issue of the exceptional access notification signal.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A multiprocessor system comprising:
 a first processor element; and   a second processor element that includes a central processing unit (CPU), a shared resource unit shared by the first and second processor elements, a protection setting unit and a guard unit,   wherein the protection setting unit sets an access protection range for the shared resource unit,   wherein the guard unit restricts an access request from the first processor element to the shared resource unit based on the access protection range,   wherein the guard unit issues an exceptional access notification signal when the access request from the first processor element is within the access protection range, and   wherein when the exceptional access notification signal is issued, the CPU extends the access protection range in such a manner that the extended access protection range is wider than the access protection range set before issue of the exceptional access notification signal.   
     
     
         2 . A multiprocessor system including a first processor element and a second processor element, the multiprocessor system comprising:
 the first processor element, comprising:
 a first shared resource unit; 
 a first protection setting unit that sets a first access protection range for the first shared resource unit; and 
 a first guard unit that restricts an access request from the second processor element to the first shared resource unit based on the first access protection range; and 
   the second processor element, comprising:
 a second shared resource unit; 
 a second protection setting unit that sets a second access protection range for the second shared resource unit; and 
 a second guard unit that restricts an access request from the first processor element to the second shared resource unit based on the second access protection range, 
   wherein when the first guard unit detects an access violation from the second processor element, the first processor element extends the first access protection range in such a manner that the first extended access protection range is wider than the first access protection range set before the detection of the access violation, and   wherein when the second guard unit detects an access violation from the first processor element, the second processor element extends the second access protection range in such a manner that the second extended access protection range is wider than the second access protection range set before the detection of the access violation.   
     
     
         3 . The multiprocessor system according to  claim 2 , the first processor element further comprising a first resource controller,
 wherein the first resource controller judges a target resource of the access request from the first processor element,   wherein the first resource controller handles the access request with the first shared resource unit when the target resource is the first shared resource unit, and   wherein the first resource controller sends the access request to the second guard unit when the target resource is the second shared resource unit.   
     
     
         4 . The multiprocessor system according to  claim 2 , the second processor element further comprising a second resource controller,
 wherein the second resource controller judges a target resource of the access request from the second processor element,   wherein the second resource controller handles the access request with the second shared resource unit when the target resource is the second shared resource unit, and   wherein the second resource controller sends the access request to the first guard unit when the target resource is the first shared resource unit.   
     
     
         5 . The multiprocessor system according to  claim 2 , wherein the first shared resource unit includes an input and/or output interface unit.

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