High performance interconnect physical layer

Abstract

A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

What is claimed is: 
     
         1 . An apparatus comprising:
 interface logic to couple to differential signal data on an interconnect, the interface logic comprising protocol logic to support cache coherent transactions and a state machine to:
 perform an exit from a first state based on a first state signal; 
 perform a primary exit from a second state based on a second state signal and a secondary exit from the second state based on second state timeout; 
 perform a primary exit from a third state based on a third state timeout. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the first state includes a first reset state and the third state includes a second reset state. 
     
     
         3 . The apparatus of  claim 1 , wherein the state machine is further to perform an exit from a fourth state based on a handshake sequence. 
     
     
         4 . The apparatus of  claim 3 , wherein the handshake sequence comprises the interface logic to send a supersequence and to validate an acknowledgement based on the supersequence. 
     
     
         5 . The apparatus of  claim 1 , wherein the state machine, when in a test mode, is capable to set the second state timeout to a value different from when the state machine is in an operational state. 
     
     
         6 . The apparatus of  claim 1 , wherein the interface logic comprises physical layer logic, link layer logic and protocol layer logic. 
     
     
         7 . The apparatus of  claim 6 , wherein at least one of the first state signal or the second state signal are to be debounced. 
     
     
         8 . The apparatus of  claim 1 , wherein the interface logic is included in a processor coupled in one socket of a server with at least two sockets. 
     
     
         9 . The apparatus of  claim 1 , wherein interface logic is included in a system on a chip (SoC). 
     
     
         10 . The apparatus of  claim 9 , wherein the SoC is coupled to a plurality of other SoCs in a micro-server. 
     
     
         11 . The apparatus of  claim 9 , further comprising a radio. 
     
     
         12 . An apparatus comprising
 a controller to interface between at least a first processor to recognize a first instruction set and second processor to recognize a second instruction set that is different from the first instruction set, the controller comprising interface logic to couple signal differentially and a state machine, wherein the state machine is to   perform an exit from a first state based on a first state signal;   perform a primary exit from a second state based on a second state signal and a secondary exit from the second state based on second state timeout;   perform a primary exit from a third state based on a third state timeout,   wherein at least one of the first state signal or the second state signal are to be debounced.   
     
     
         13 . The apparatus of  claim 12 , wherein the state machine is further to perform an exit from a fourth state based on a handshake sequence. 
     
     
         14 . The apparatus of  claim 13 , wherein the handshake sequence comprises the interface logic to send a supersequence and to validate an acknowledgement. 
     
     
         15 . The apparatus of  claim 12 , wherein the first and the second processor are coupled to the controller. 
     
     
         16 . The apparatus of  claim 15 , wherein the first instruction set comprises an Intel® based instruction set. 
     
     
         17 . A computer readable medium including code, when executed, to cause interface logic that is to couple to a serial, differential interconnect to:
 perform an exit from a first state based on a first state signal;   perform a primary exit from a second state based on a second state signal and a secondary exit from the second state based on second state timeout;   perform a primary exit from a third state based on a third state timeout,   
     
     
         18 . The computer readable medium of  claim 17 , wherein the state machine is further to perform an exit from a fourth state based on a handshake sequence. 
     
     
         19 . The computer readable medium of  claim 18 , wherein the handshake sequence comprises the interface logic to send a supersequence and to validate an acknowledgement. 
     
     
         20 . The computer readable medium of  claim 17 , wherein the first state includes a first reset state and the third state includes a second reset state.