Package interconnects

Abstract

A method for forming a device is disclosed. A substrate having first and second major surfaces is provided. A stress buffer is formed in the substrate. A through silicon via (TSV) contact is formed between the stress buffer. The stress buffer has a depth less than a depth of the TSV contact. The stress buffer alleviates stress created by the difference in coefficient thermal expansion (CTE) between the TSV contact and the substrate.

What is claimed is: 
     
         1 . A device comprising:
 a semiconductor substrate having first and second major surfaces;   a stress buffer filled with stress buffer material in the semiconductor substrate; and   a through silicon via (TSV) contact disposed in the substrate, the TSV contact has first and second portions, the second portion extends beyond a bottom of the stress buffer, wherein the stress buffer completely surrounds the first portion of the TSV contact and alleviates stress created by the difference in coefficient of thermal expansion (CTE) between the TSV contact and the semiconductor substrate.   
     
     
         2 . The device of  claim 1  wherein a bottom of the TSV contact extends to the second major surface of the substrate. 
     
     
         3 . The device of  claim 1  comprising:
 an ILD layer disposed on the first major surface of the semiconductor substrate; and 
 the TSV contact is disposed in the ILD layer and the semiconductor substrate. 
 
     
     
         4 . The device of  claim 3  wherein a bottom of the TSV contact extends to the second major surface of the substrate. 
     
     
         5 . The device of  claim 1  wherein:
 the first major surface of the semiconductor substrate comprises an ILD layer; 
 the stress buffer trench is disposed in the ILD layer and the semiconductor substrate; and 
 the TSV contact is disposed in the ILD layer and the semiconductor substrate. 
 
     
     
         6 . The device of  claim 5  wherein a bottom of the TSV contact extends to the second major surface of the substrate. 
     
     
         7 . The device of  claim 1  wherein the stress buffer is disposed on the first major surface of the semiconductor substrate. 
     
     
         8 . The device of  claim 7  wherein the first major surface of the semiconductor substrate further comprises an ILD layer, and the TSV contact is disposed in the ILD layer and the semiconductor substrate. 
     
     
         9 . The device of  claim 1  wherein the stress buffer is displaced from the TSV contact. 
     
     
         10 . The device of  claim 9  wherein the stress buffer material comprises material having elastic modulus less than about 100 GPa. 
     
     
         11 . The device of  claim 9  wherein the stress buffer material comprises polymer, plastic, organic or inorganic dielectrics, porous dielectric material or a combination thereof 
     
     
         12 . The device of  claim 1  wherein the TSV contact is disposed in the substrate through the stress buffer, and the first portion of the TSV contact abuts the stress buffer. 
     
     
         13 . The device of  claim 12  wherein the stress buffer material comprises material having elastic modulus less than about 100 GPa. 
     
     
         14 . The device of  claim 13  wherein the stress buffer material comprises polymer, plastic, organic or inorganic dielectrics, porous dielectric material or a combination thereof 
     
     
         15 . The device of  claim 1  further comprising a plurality of stress buffers and a plurality of TSV contacts. 
     
     
         16 . A device comprising:
 a semiconductor substrate having first and second major surfaces, the substrate includes an isolation region disposed in a first substrate region of the substrate, wherein the isolation region extends partially through the substrate and is filled with isolation material;   a stress buffer filled with stress buffer material in a second substrate region of the substrate; and   a through silicon via (TSV) contact disposed in the second substrate region of the substrate, the TSV contact has first and second portions, the second portion extends beyond a bottom of the stress buffer, wherein the stress buffer material completely surrounds the first portion of the TSV contact and alleviates stress created by the difference in CTE between the TSV contact and the semiconductor substrate.   
     
     
         17 . The device of  claim 16  comprising:
 an ILD layer on the first major surface of the semiconductor substrate; and 
 the TSV contact is disposed in the first substrate region in the ILD layer and the semiconductor substrate. 
 
     
     
         18 . The device of  claim 17  wherein the stress buffer is disposed in the ILD layer and the semiconductor substrate. 
     
     
         19 . The device of  claim 16  wherein the stress buffer does not abut the TSV contact. 
     
     
         20 . The device of  claim 16  wherein the TSV contact abuts the stress buffer.