Beol compatible fet structure

Abstract

This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

What is claimed is: 
     
         1 . An electrical interconnect structure having thin film transistors comprising:
 a first dielectric containing a plurality of conductors wherein some of said conductors form conducting lines and/or vias, and other conductors form gate electrodes of said thin film transistors;   an insulating material atop said gate electrodes;   a semiconductor having spaced-apart doped source and drain regions with a channel disposed there between atop said insulating material, wherein said semiconductor is a polycrystalline semiconductor formed at temperatures below 450° C.;   a second dielectric having a plurality of conductors where some conductors form conducting lines and/or vias, and other conductors form contacts to said source and drain regions of said thin film transistors; and   at least one of
 a second gate electrode above said semiconductor region; 
 an insulating material between said semiconductor region and said second gate electrode covering the entire surface of the semiconductor material and/or surrounding the bottom and sidewalls of said gate electrode; and optionally 
 a conducting diffusion barrier liner on at least one side of said gate electrode. 
   
     
     
         2 . The electrical interconnect structure of  claim 1 , further comprising: a conducting or insulating diffusion barrier atop said metal gate electrodes and said metal lines and vias, wherein said insulating diffusion barrier comprises a material selected from the group consisting of: SiN, materials containing Si, C, N, and H, materials containing Si, C, and H, and insulating materials that have barrier properties that inhibit diffusion of the gate metal. 
     
     
         3 . The electrical interconnect structure of  claim 2 , wherein said diffusion barrier is a continuous, insulating diffusion barrier atop both of said metal conductors and said first dielectric. 
     
     
         4 . The electrical interconnect structure of  claim 2 , wherein said diffusion barrier is a conducting diffusion barrier, and wherein said conducting diffusion barrier is disposed selectively atop said metal conductors, not atop said first dielectric. 
     
     
         5 . The electrical interconnect structure of  claim 2 , wherein said insulating diffusion barrier is said insulating material atop said metal gate electrode. 
     
     
         6 . The electrical interconnect structure of  claim 1 , wherein said first dielectric layer and second dielectric layer can be the same or different materials selected from the group consisting of: an insulating oxide, a low k dielectric material, a porous low k dielectric material, and a dielectric containing air gaps. 
     
     
         7 . The electrical interconnect structure of  claim 1 , wherein said conducting line and/or vias have a metal selected from the group consisting of: Cu, Al, W, and Ag; said gate electrode has a metal selected from the group consisting of: Cu, Al, W, Ag, Er, Ni, Co, Au, Sn, poly-Si, and poly-Ge, and said source and drain contacts have a metal selected from the group consisting of: Cu, Al, W, Ag, Er, Ni, Co, Au, and Sn. 
     
     
         8 . The electrical interconnect structure of  claim 2 , wherein said conducting diffusion barrier comprises a material selected from the group consisting of: TiN, TaN, TiSiN, metal nitrides, metal silicon nitrides, conductive metal carbides, Ti, Ta, W, WN, Cr, Nb and combinations thereof. 
     
     
         9 . The electrical interconnect structure of  claim 1 , wherein said semiconductor material is a polycrystalline material with a bulk mobility of greater than 100 cm 2 /Vs, comprising a material selected from the group consisting of: a polycrystalline Ge, polycrystalline SiGe, CdSe, polycrystalline Si, amorphous Si, amorphous Ge, these materials further including carbon, InAs, InAlAs, InGaAs, and other III-V compounds. 
     
     
         10 . The electrical interconnect structure of  claim 1 , wherein said spaced apart doped source and drain regions comprise a material selected from the group consisting of: B, As, P, Ga, In, Al, and Zn. 
     
     
         11 . The electrical interconnect structure of  claim 5 , wherein said conducting diffusion barrier selectively disposed atop said metal conductors comprises a material selected from the group consisting of: CoWP, Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN, TaSiN, and combinations thereof. 
     
     
         12 . The electrical interconnect structure of  claim 1 , wherein said insulating material atop said gate electrode is comprised of one or more layers comprising a material selected from the group consisting of: SiO 2 , silicon nitride, silicon oxynitride, silicon-containing oxides, insulating metal oxides, insulating metal nitrides, insulating metal silicon oxides, insulating metal silicon oxynitrides, germanium oxynitride, germanium-containing oxide, insulating metal germanium oxides, insulating metal germanium oxynitrides, materials containing Si, C, N, and H; SiN, and materials containing Si, C, and H.