Memory device and memory system with sensor

Abstract

According to one embodiment, a memory device includes a first address memory storing a first address; a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command.

What is claimed is: 
     
         1 . A memory device comprising:
 a first address memory storing a first address;   a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and   a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command.   
     
     
         2 . The device of  claim 1 , wherein:
 the controller does not transmit an address to which a write by the first command is executed after transmission of the first command.   
     
     
         3 . The device of  claim 2 , wherein:
 the first interface requests a circuit based on the first interface to transmit a command, an address, and data on one signal line.   
     
     
         4 . The device of  claim 1 , wherein:
 the controller outputs a second command and a write address in accordance with the first interface, and   the first address memory stores the write address as the first address when the second command is received.   
     
     
         5 . The device of  claim 1 , wherein:
 the controller outputs a second command in accordance with the first interface, and   the first address memory outputs the first address when the second command is received.   
     
     
         6 . The device of  claim 1 , wherein:
 the device further comprises a second address memory which stores a second address,   the controller outputs a second command in accordance with the first interface, and   the memory outputs data stored in an address based on the second address when the memory receives the second command.   
     
     
         7 . The device of  claim 6 , wherein:
 the memory consecutively outputs data stored in an address based on the second address and one or more subsequent addresses while the memory keeps receiving an enable signal after the memory receives the second command.   
     
     
         8 . The device of  claim 6 , wherein:
 when the memory receives the second command, the memory outputs data stored in the address based on the second address after a lapse of a period from the receipt of the second command.   
     
     
         9 . The device of  claim 6 , wherein
 the controller outputs a third command and a read address in accordance with the first interface, and   the second address memory stores the read address as the second address memory when the third command is received.   
     
     
         10 . The device of  claim 6 , wherein:
 the controller outputs a third command in accordance with the first interface, and   the second address memory outputs the second address when the third command is received.   
     
     
         11 . The device of  claim 1 , wherein:
 the memory comprises a magnetic random access memory.   
     
     
         12 . The device of  claim 1 , further comprising:
 an output circuit which receives data from the memory at a first frequency and outputs the received data to outside the memory device at a second frequency higher than the first frequency.   
     
     
         13 . A memory device comprising:
 memory cells which store data in a nonvolatile manner;   an error correction circuit which:
 receives write data, 
 uses the write data and a first matrix to execute an operation to generate parity, 
 receives read data and parity based on from the read data, 
 uses the read data, the parity based on the read data and a second matrix to generate a syndrome, 
 uses the syndrome to correct an error of the read data, 
 wherein the second matrix includes the first matrix and a unit matrix, and 
 the first matrix comprises components selected such that an XOR of any two columns of the second matrix is different from an XOR of any other two columns and any column of the second matrix; and 
   a controller which writes the write data and the parity based on the write data in memory cells, and supplies the read data and the parity based on the read data from memory cells to the error corrections circuit.   
     
     
         14 . The device of  claim 13 , wherein:
 the first matrix comprises components in eight rows and eight columns, and   the second matrix comprises components in eight rows and sixteen columns.   
     
     
         15 . The device of  claim 14 , wherein:
 the write data comprises components in eight rows and one column, and   the error correction circuit multiplies the first matrix and the write data to generate parity of eight rows and one column.   
     
     
         16 . The device of  claim 14 , wherein:
 the second matrix comprises the first matrix in first to eighth columns and a unit matrix in ninth to sixteenth columns,   the read data comprises components in eight rows and one column,   the error correction circuit multiplies the second matrix and an input which comprises the read data in first to eighth columns and the parity based on the read data in ninth to sixteenth columns to generate the syndrome, and   the syndrome comprises components in eight rows and one column.   
     
     
         17 . The device of  claim 16 , wherein:
 the first matrix comprises only components of one or zero, and   when the input has an error in a k th  column (k being a natural number not greater than sixteen), the syndrome is the same as a k th  column of the second matrix.   
     
     
         18 . The device of  claim 17 , wherein:
 when the input has errors in a k th  column and h th  column (h being a natural number different from k and not greater than sixteen), the syndrome is the same as an XOR of a k th  column and an h th  column of the second matrix.   
     
     
         19 . The device of  claim 14 , wherein:
 the first matrix comprises:
 in an n th  row in an m th  column, the same component as a component in an (n+1) th  row in an (m+1) th  column; and 
 in an eighth row in the m th  column, the same component as a component in a first row in an (m+1) th  column, 
   where each of m and n is a natural number not greater than seven.