Semiconductor Device Having Multi-Level Wiring Structure

Abstract

Disclosed herein is a device that includes a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer; a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers; a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction; and a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a memory mat including a plurality of memory cells;   a sense amplifier located in a sense amplifier area and amplifying data supplied from the memory cells to generate first amplified data;   a main amplifier that amplifies the first amplified data supplied from the sense amplifier;   a main I/O line extends in a first direction to connect the sense amplifier to the main amplifier, the main I/O line including a first section provided over the memory mat as a first wiring layer and the second section provided over the sense amplifier area as a third wiring layer different from the first wiring layer;   a power-supply line provided as the third wiring layer such that the power-supply line overlaps with the first section of the main I/O line;   a sub-word line extending in a second direction, which is crossing to the first direction, and being connected to the plurality of memory cells;   a sub-word driver driving a corresponding one of the sub-word lines and placed between the memory mats; and   a main word line extending in the second direction and being connected to the sub-word driver.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , further comprising a local I/O line provided over the sense amplifier area and extending in a second direction crossing the first direction to connect the sense amplifier to the main I/O line,
 wherein the local I/O line is provided as a second wiring layer that is between the first wiring layer and the third wiring layer.   
     
     
         3 . The semiconductor device as claimed in  claim 2 , the main word line is provided in the second wiring layer. 
     
     
         4 . The semiconductor device as claimed in  claim 3 , further comprising:
 a column switch that connects the sense amplifier to the local I/O line; and   a column selection line controlling the column switch, the column selection line being provided as the first wiring layer over the memory mat.   
     
     
         5 . The semiconductor device as claimed in  claim 4 , wherein the column selection line has a roundabout pattern to avoid contacting the first section of the main I/O line in the first wiring layer. 
     
     
         6 . A semiconductor device comprising:
 a memory mat having a plurality of bit lines each extending in a first direction, a plurality of sub-word lines extending in a second direction crossing to the first direction, and a plurality of memory cells arranged respectively at intersections of the bit lines and the word lines;   a plurality of sense amplifiers coupled respectively to the bit lines, the sense amplifiers being provided in a sense amplifier area that is adjacent to the memory mat in the first direction;   a plurality of column selection lines extending in the first direction as a first wiring layer;   a local I/O line extending in the second direction as a second wiring layer;   a plurality of main I/O lines extending in the first direction, the main I/O lines being provided as a third wiring layer over the sense amplifier area and provided as the first wiring layer over the memory mat;   a power-supply line extending in the first direction as the third wiring layer, a part of the power-supply line overlapping with the main I/O lines provided over the memory mat;   a sub-word driver driving a corresponding one of the sub-word lines and placed between the memory mats; and   a main word line extending in the second direction in a third wiring layer and being connected to the sub-word driver.   
     
     
         7 . The semiconductor device as claimed in  claim 6 , wherein an arrangement pitch of the column selection lines over the memory mat is narrower than an arrangement pitch thereof over the sense amplifier area to secure an empty space on the first wiring layer, the main I/O lines are arranged in the empty space in the first wiring layer over the memory mat. 
     
     
         8 . The semiconductor device as claimed in  claim 7 , wherein the column selection lines have a roundabout pattern to form the empty space on a central part of the memory mat in the second direction. 
     
     
         9 . The semiconductor device as claimed in  claim 7 , herein the column selection lines have a roundabout pattern to form the empty space on an end side of the memory mat in the second direction. 
     
     
         10 . The semiconductor device as claimed in  claim 6 , further comprising a plurality of contact plugs each connected between an associated one of the main I/O lines provided as the first wiring layer and the associated one of the main I/O lines provided as the third wiring layer. 
     
     
         11 . The semiconductor device as claimed in  claim 6 , wherein two column selection lines are arranged between adjacent two main I/O lines formed as the first wiring layer over the memory mat. 
     
     
         12 . The semiconductor device as claimed in  claim 6 , wherein
 the power-supply line includes a first section that overlapping with the main I/O lines and a plurality of second sections elongated from the first section to the first direction, each of the second section is narrower in width than the first section,   the main I/O lines and the second sections of the power-supply line are alternately arranged in the second direction on the first wiring layer, and   the first and second sections of the power-supply line are short-circuited to constitute a single line that extends in the first direction.   
     
     
         13 . The semiconductor device as claimed in  claim 6 , wherein the power-supply line is supplied with an external power-supply potential. 
     
     
         14 . A device comprising:
 a multi-level wiring structure including a first wiring layer and a second wiring layer formed over the first wiring layer;   a memory cell array area including a plurality of memory cells, a plurality of sense amplifiers and a plurality of sub amplifiers;   a main amplifier area including a plurality of main amplifiers, the memory cell array area and the main amplifier area being arranged in line in a first direction;   a plurality of first I/O lines each connecting an associated one of the sub amplifiers to an associated one of the main amplifiers, each of the first I/O lines including first and second wiring portions that are elongated in the first direction, the first wiring portion being formed as the first wiring layer and the second wiring portion being formed as the second wiring layer;   a sub-word line extending in a second direction, which is crossing to the first direction, and being connected to the plurality of memory cells;   a sub-word driver driving a corresponding one of the sub-word lines and placed between the memory mats; and   a main word line extending in the second direction in a third wiring layer and being connected to the sub-word driver.   
     
     
         15 . The device as claimed in  claim 14 , wherein the memory cell array area including first and second regions arranged in line in the first direction, each of the first and second regions includes first and second parts arranged in line in a second direction crossing to the first direction, the memory cells includes a first set of memory cells disposed in the first part of the first region, the sense amplifier includes a first set of sense amplifiers disposed in the first part of the second region, the sub amplifier includes a first sub amplifier disposed in the second part of the second region, the first wiring portion of each of the first I/O lines is formed over the first part of the second region, and the second wiring portion of each of the first I/O lines is formed over the first part of the first region. 
     
     
         16 . The device as claimed in  claim 15 , wherein the memory cell array area further includes a set of word line drivers disposed in the second part of the first region. 
     
     
         17 . The device as claimed in  claim 14 , wherein the multi-level wiring structure further includes a third wiring layer formed between the first and the second wiring layers, the device further comprises a plurality of second I/O lines each elongated in a second direction crossing to the first direction, each of the second I/O lines connected corresponding ones of the sense amplifiers to a corresponding one of sub amplifiers. 
     
     
         18 . The device as claimed in  claim 17 , wherein the memory cell array area including first and second regions arranged in line in the first direction, each of the first and second regions includes first and second parts arranged in line in a second direction crossing to the first direction, the memory cells includes a first set of memory cells disposed in the first part of the first region, the sense amplifier includes a first set of sense amplifiers disposed in the first part of the second region, the sub amplifier includes a first sub amplifier disposed in the second part of the second region, the first wiring portion of each of the first I/O lines is formed over the first part of the second region, the second wiring portion of each of the first I/O lines is formed over the first part of the first region, and the second I/O lines are formed over the first part of the second region. 
     
     
         19 . The device as claimed in  claim 18 , wherein the memory cell array area further includes a set of word line drivers disposed in the second part of the first region. 
     
     
         20 . The device as claimed in  claim 14 , wherein the memory cell array area including a plurality of first regions and a plurality of second regions arranged in line in the first direction, each of the second regions is between associated two of the first regions, each of the first regions and each of the second regions includes first and second parts arranged in line in a second direction crossing to the first direction, the first part of each of the first regions includes associated ones of the memory cells, the first part of the each of the second regions includes associated ones of the sense amplifiers, the second part of each of the second region includes an associated one of the sub amplifiers, each of the first I/O lines further includes a plurality of third wiring portions each elongated in the first direction and formed as the first wiring layer and a plurality of fourth wiring portions each elongated in the first direction and formed as the second wiring layer, each of the first and third wiring portions of each of the first I/O lines is formed over the first part of a corresponding one of the second regions, and each of the second and third wiring portions of each of the first I/O lines is formed over the first part of a corresponding one of the first regions.