Late in-situ doped sige junctions for pmos devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Abstract

A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.

What is claimed is: 
     
         1 . A device comprising:
 first and second high-k dielectric metal gate (HKMG) gate stacks;   a nitride liner in direct contact with first and second oxide spacers on each side of each of the first and second HKMG gate stacks;   halo and extension regions at opposite sides of each of the first and second HKMG gate stacks;   deep source/drain regions at opposite sides of the second gate HKMG gate stack; and   embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack.   
     
     
         2 . The device according to  claim 1 , wherein nitride spacers are formed over the second oxide spacers, and the deep source/drain regions at opposite sides of the second gate HKMG gate stack formed using the nitride spacers as a soft mask. 
     
     
         3 . The device according to  claim 2 , wherein the nitride liner and nitride spacers comprise silicon nitride (SiN). 
     
     
         4 . The device according to  claim 3 , wherein the oxide spacers comprise silicon dioxide (SiO 2 ). 
     
     
         5 . The device according to  claim 1 , wherein the eSiGe is doped in-situ with boron having a graded doping profile. 
     
     
         6 . The device according to  claim 1 , further comprising a silicide on the eSiGe, the deep source/drain regions, and the first and second HKMG gate stacks. 
     
     
         7 . The device according to  claim 1 , further comprising a channel SiGe region below the first HKMG gate stack. 
     
     
         8 . The device according to  claim 1 , wherein each of the first and second HKMG gate stacks comprises a high-k dielectric, a work function metal, and polysilicon (poly-Si). 
     
     
         9 . The device according to  claim 1 , wherein the embedded eSiGe is embedded by forming a cavity and epitaxially growing SiGe in the cavity. 
     
     
         10 . The device according to  claim 9 , wherein the cavity is formed by wet etching with tetramethylammonium hydroxide (TMAH). 
     
     
         11 . A device comprising:
 PMOS and NMOS high-k metal gate (HKMG) gate stacks on a substrate;   a first L-shaped liner and first spacers on each side of each of the PMOS and NMOS HKMG gate stacks, such that the first L-shaped liner is in direct contact with the PMOS and NMOS HKMG gate stacks;   halo/extension implants at each side of each of the PMOS and NMOS HKMG gate stacks;   a second L-shaped liner and second spacers on the first spacers of each of the PMOS and NMOS HKMG gate stacks;   deep source/drain regions at opposite sides of the NMOS HKMG gate stack; embedded silicon germanium (eSiGe) at opposite sides of the PMOS HKMG gate stack; and   a silicide on the source/drain regions, the eSiGe, and the PMOS and NMOS HKMG gate stacks.   
     
     
         12 . The device according to  claim 11 , wherein the first L-shaped liner comprises silicon nitride (SiN). 
     
     
         13 . The device according to  claim 11 , wherein the first spacers comprise silicon dioxide (SiO2). 
     
     
         14 . The device according to  claim 11 , wherein the second L-shaped liner comprises silicon dioxide (SiO2). 
     
     
         15 . The device according to  claim 11 , wherein the second spacers comprise silicon nitride (SiN). 
     
     
         16 . The device according to  claim 11 , wherein the embedded eSiGe is embedded by forming a cavity and epitaxially growing SiGe in the cavity. 
     
     
         17 . The device according to  claim 16 , wherein a boron dopant, with a graded doping profile, is implanted in-situ into the eSiGe concurrently with the epitaxial growth. 
     
     
         18 . The device according to  claim 16 , wherein the cavity is formed by wet etching with tetramethylammonium hydroxide (TMAH). 
     
     
         19 . The device according to  claim 18 , wherein the cavity is sigma shaped. 
     
     
         20 . The device according to  claim 11 , wherein each of the PMOS and NMOS HKMG gate stacks comprises a high-k dielectric, a work function metal, and polysilicon (poly-Si).