Semiconductor device and method of manufacturing the same

Abstract

Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region.

1 - 67 . (canceled) 
     
     
         68 . A semiconductor device including a memory cell of a non-volatile memory comprising:
 a semiconductor substrate having a memory cell forming region and a power supplying region;   a first gate insulating film formed over the semiconductor substrate;   a first gate electrode formed over the semiconductor substrate via the first gate insulating film for forming the memory cell;   a first insulating film formed over the first gate electrode;   a second gate electrode formed over the semiconductor substrate so as to be adjacent to the first gate electrode in a first direction for forming the memory cell;   a second gate insulating film having a charge storage portion inside formed between the second gate electrode and the semiconductor substrate and between the first gate electrode and the second gate electrode;   an interlayer insulating film formed over the semiconductor substrate so as to cover the memory cell;   a first plug which supplies a potential to the first gate electrode and which is formed in the interlayer insulating film;   a second plug which supplies a potential to the second gate electrode and which is formed in the interlayer insulating film,   wherein the second gate electrode is formed over a sidewall of a stacked film pattern formed of the first gate electrode and the first insulating film,   wherein the first gate electrode, the first insulating film, and the second gate electrode are formed so as to extend in a second direction orthogonal to the first direction,   wherein the first gate electrode is formed in the power supplying region and includes a first contact portion connected to the first plug,   wherein a first metal silicide layer is formed in at least a part of an upper surface of the first contact portion which is not covered by the first insulating film,   wherein the first metal silicide layer is not formed in a part of an upper surface of the first gate electrode which is covered by the first insulating film,   wherein the second gate electrode is formed in the power supplying region and includes a second contact portion connected to the second plug,   wherein the second contact portion extends in a direction away from the first gate electrode from a position adjacent to the sidewall of the first gate electrode,   wherein the second contact portion does not extend over the first insulating film, and   wherein the second metal silicide layer is formed in an upper portion of the second gate electrode.   
     
     
         69 . The semiconductor device according to  claim 68 ,
 wherein a length of the second contact portion in the first direction is greater than a length of the second gate electrode in the memory cell forming region.   
     
     
         70 . The semiconductor device according to  claim 68 ,
 wherein the second contact portion extends in the first direction.   
     
     
         71 . The semiconductor device according to  claim 68 ,
 wherein the first contact portion extends in a direction away from the second gate electrode.   
     
     
         72 . The semiconductor device according to  claim 71 ,
 wherein a length of the first contact portion in the first direction is greater than a length of the first gate electrode in the memory cell forming region.   
     
     
         73 . The semiconductor device according to  claim 68 , further comprising:
 a first wiring formed over the interlayer insulating film and electrically connected to the first contact portion via the first plug; and   a second wiring formed over the interlayer insulating film and electrically connected to the second contact portion via the second plug.   
     
     
         74 . The semiconductor device according to  claim 68 ,
 wherein a device isolation region is formed in the semiconductor substrate, and   wherein the first contact portion and the second contact portion are formed over the device isolation region.   
     
     
         75 . The semiconductor device according to  claim 68 ,
 wherein the second gate electrode formed over the memory cell forming region is formed in a sidewall spacer shape over one sidewall of the first gate electrode.