Vertical iii-v nanowire field-effect transistor using nanosphere lithography

Abstract

A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process.

1 . A semiconductor device, comprising:
 a drain contact;   a plurality of nanopillars directly connected to said drain contact, wherein each of said plurality of nanopillars comprises a channel of said semiconductor device, wherein each of said plurality of channels comprises undoped III-V semiconductor material;   a gate dielectric layer surrounding said plurality of nanopillars;   a gate contact connected to a gate metal layer which is connected to said gate dielectric layer;   a substrate connected to said plurality of nanopillars via a first layer of doped III-V semiconductor material, wherein said gate metal layer is isolated from said first layer of doped III-V semiconductor material by said gate dielectric layer; and   a source contact directly connected to said substrate.   
     
     
         2 . The semiconductor device as recited in  claim 1 , wherein each of said plurality of nanopillars comprises a second layer of doped III-V semiconductor material. 
     
     
         3 . The semiconductor device as recited in  claim 2 , wherein said first and second layers of doped III-V semiconductor material comprises doped indium gallium arsenide. 
     
     
         4 . The semiconductor device as recited in  claim 1 , wherein said undoped III-V semiconductor material comprises undoped indium gallium arsenide. 
     
     
         5 . The semiconductor device as recited in  claim 1 , wherein a perimeter of said plurality of nanopillars controls a diameter of said plurality of channels. 
     
     
         6 . The semiconductor device as recited in  claim 1 , wherein a length of each of said plurality of channels is between 50 nm and 200 nm. 
     
     
         7 . The semiconductor device as recited in  claim 1 , wherein a diameter of each of said plurality of channels is approximately 150 nm. 
     
     
         8 . The semiconductor device as recited in  claim 1 , wherein said substrate comprises doped III-V semiconductor material. 
     
     
         9 . The semiconductor device as recited in  claim 8 , wherein said substrate comprises indium phosphide. 
     
     
         10 . The semiconductor device as recited in  claim 1 , wherein said gate metal comprises titanium nitride. 
     
     
         11 . A method for fabricating a vertical III-V nanowire field-effect transistor, the method comprising:
 depositing a first layer of doped III-V semiconductor material on a substrate of III-V semiconductor material;   depositing a layer of undoped III-V semiconductor material on top of said first layer of doped III-V semiconductor material;   depositing a second layer of doped III-V semiconductor material on top of said layer of undoped III-V semiconductor material;   growing a first dielectric layer on top of said second layer of doped III-V semiconductor material;   depositing self-assembled monolayers of nanospheres on said first dielectric layer; and   forming nanopillars using said nanospheres as a mask and said first dielectric layer as a hard mask to etch said second layer of doped III-V semiconductor material and said layer of undoped III-V semiconductor material using nanosphere lithography.   
     
     
         12 . The method as recited in  claim 11 , wherein said first dielectric layer comprises silicon dioxide. 
     
     
         13 . The method as recited in  claim 11 , wherein a diameter of said nanospheres is controlled via oxygen plasma. 
     
     
         14 . The method as recited in  claim 11  further comprising:
 dry etching said nanospheres and said first dielectric layer to remove said nanospheres and said first dielectric layer. 
 
     
     
         15 . The method as recited in  claim 14  further comprising:
 depositing a second dielectric layer over said nanopillars and a remaining portion of said first layer of doped III-V semiconductor material that is exposed following said dry etching. 
 
     
     
         16 . The method as recited in  claim 15  further comprising:
 depositing a gate metal over said second dielectric layer; and 
 depositing a third dielectric layer over said gate metal. 
 
     
     
         17 . The method as recited in  claim 16  further comprising:
 etching said third dielectric layer to expose said gate metal; and 
 etching a portion of said gate metal and a portion of said second dielectric layer to expose a top portion of said nanopillars. 
 
     
     
         18 . The method as recited in  claim 17  further comprising:
 removing a remaining portion of said third dielectric layer to expose a portion of said gate metal; 
 depositing a fourth dielectric layer over said exposed nanopillars and said exposed gate metal; and 
 depositing a photoresist layer over a portion of said fourth dielectric layer. 
 
     
     
         19 . The method as recited in  claim 18  further comprising:
 etching said fourth dielectric layer according to a pattern in said photoresist layer in order to form a drain contact; and 
 etching a portion of said fourth dielectric layer to form a gate contact. 
 
     
     
         20 . The method as recited in  claim 19  further comprising;
 adding a source contact to a bottom of said substrate.