Integrated circuit and manufacturing method thereof

Abstract

An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device.

1 - 23 . (canceled) 
     
     
         24 . An integrated circuit, comprising:
 an analog block for receiving a radio frequency signal and outputting an operation command signal;   a digital block for generating and outputting an address and an operation control signal according to the operation command signal from the analog block and outputting a response signal corresponding to the operation command signal to the analog block; and   a memory block for receiving the operation control signal, generating an internal signal, and reading/writing data on a nonvolatile ferroelectric capacitor device according to the internal signal,   wherein a ferroelectric capacitance unit having a ferroelectric capacitor device is formed on an upper layer of a peripheral circuit region.   
     
     
         25 . The integrated circuit according to  claim 24 , wherein the ferroelectric capacitance unit is shared by the peripheral circuit region. 
     
     
         26 . The integrated circuit according to  claim 24 , wherein metal lines allocated to the ferroelectric capacitance unit are disconnected from the ferroelectric capacitor device when the ferroelectric capacitor device is not used. 
     
     
         27 . The integrated circuit according to  claim 24 , wherein the peripheral circuit region is a CMOS circuit region comprising of active and passive devices including a CMOS. 
     
     
         28 . The integrated circuit according to  claim 27 , wherein the ferroelectric capacitance unit is formed using a lamination process at the upper layer of the CMOS circuit region. 
     
     
         29 . An integrated circuit, comprising:
 an analog block for receiving a radio frequency signal, and outputting an operation command signal;   a digital block for generating and outputting an address and an operation control signal according to the operation command signal from the analog block, and outputting a corresponding response signal to the analog block; and   a memory block for receiving the operation control signal, generating an internal adjustment signal, and reading/writing data on a nonvolatile ferroelectric capacitor device according to the internal adjustment signal,   wherein a ferroelectric capacitance unit having a ferroelectric capacitor device is formed on an upper layer of the analog block.   
     
     
         30 . The integrated circuit according to  claim 29 , wherein the ferroelectric capacitance unit is shared by the analog block. 
     
     
         31 . The integrated circuit according to  claim 30 , wherein the analog block is a CMOS region comprising of active and passive devices including a CMOS. 
     
     
         32 . The integrated circuit according to  claim 29 , wherein metal lines allocated to the ferroelectric capacitance unit are disconnected from the ferroelectric capacitor device when the ferroelectric capacitor device is not used. 
     
     
         33 . The integrated circuit according to  claim 29 , wherein the ferroelectric capacitance unit is formed using a lamination process. 
     
     
         34 . An integrated circuit, comprising:
 an analog block for receiving a radio frequency signal, and outputting an operation command signal;   a digital block for generating and outputting an address and an operation control signal according to the operation command signal from the analog block, and outputting a corresponding response signal to the analog block; and   a memory block for receiving the operation control signal, generating an internal adjustment signal, and reading/writing data on a nonvolatile ferroelectric capacitor device according to the internal adjustment signal,   wherein a ferroelectric capacitance unit having a ferroelectric capacitor device is formed on an upper layer of the digital block.   
     
     
         35 . The integrated circuit according to  claim 34 , wherein the ferroelectric capacitance unit is shared by the digital block. 
     
     
         36 . The integrated circuit according to  claim 34 , wherein metal lines allocated to the ferroelectric capacitance unit are disconnected from the ferroelectric capacitor device when the ferroelectric capacitor device is not used. 
     
     
         37 . The integrated circuit according to  claim 34 , wherein the digital block is a CMOS region comprising of active and manual devices including a CMOS. 
     
     
         38 . The integrated circuit according to  claim 34 , wherein the ferroelectric capacitance unit is formed using a lamination process. 
     
     
         39 - 59 . (canceled)