Arithmetic processing device and control method of arithmetic processing device

Abstract

An arithmetic processing device includes: a first instruction execution unit configured to include plural staging latches and execute a first instruction by a pipeline operation requiring only a single clock for transition of data between first plural staging latches including a staging latch at a final stage from among the plural staging latches, and a multi-cycle operation requiring plural clocks for transition of data between second plural staging latches positioning at a previous stage side than the first plural staging latches from among the plural staging latches; a second instruction execution unit configured to execute a second instruction; and an instruction control unit configured to input the first instruction and the second instruction, issue the first instruction to the first instruction execution unit and issue the second instruction to the second instruction execution unit such that the execution of the first instruction and the second instruction are partly overlapped.

What is claimed is: 
     
         1 . An arithmetic processing device, comprising:
 a first instruction execution unit configured to include plural staging latches and execute a first instruction by a pipeline operation requiring only a single clock for transition of data between first plural staging latches including a staging latch at a final stage from among the plural staging latches, and a multi-cycle operation requiring plural clocks for transition of data between second plural staging latches positioning at a previous stage side than the first plural staging latches from among the plural staging latches;   a second instruction execution unit configured to execute a second instruction; and   an instruction control unit configured to input the first instruction and the second instruction, issue the first instruction to the first instruction execution unit and issue the second instruction to the second instruction execution unit such that the execution of the first instruction and the execution of the second instruction are partly overlapped.   
     
     
         2 . The arithmetic processing device according to  claim 1 ,
 wherein the second instruction execution unit includes plural second staging latches, and executes the second instruction by a pipeline operation requiring only a single clock for transition of data between third plural staging latches including a staging latch at a first stage from among the plural second staging latches, and a multi-cycle operation requiring plural clocks for the transition of data between fourth plural staging latches positioning at a subsequent step side than the third plural staging latches from among the plural second staging latches.   
     
     
         3 . The arithmetic processing device according to  claim 1 ,
 wherein the second instruction execution unit includes plural second staging latches, and executes the second instruction by an unshared multi-cycle operation requiring plural clocks for transition of data between the plural second staging latches and circuits each positioning between the plural second staging latches are not shared with circuits held by the other instruction execution unit included by the arithmetic processing device.   
     
     
         4 . The arithmetic processing device according to  claim 1 ,
 wherein the second instruction execution unit includes plural second staging latches, and executes the second instruction by an unshared pipeline operation requiring only a single clock for transition of data between third plural staging latches including a staging latch at a first stage from among the plural second staging latches and circuits each positioning between the third plural staging latches are not shared with circuits held by the other instruction execution unit included by the arithmetic processing device, and a shared pipeline operation requiring only a single clock for transition of data between fourth plural staging latches positioning at a subsequent stage side than the third plural staging latches from among the plural second staging latches and circuits each positioning between the fourth plural staging latches are shared with circuits held by the other instruction execution unit included by the arithmetic processing device.   
     
     
         5 . The arithmetic processing device according to  claim 1 ,
 wherein the instruction control unit suppresses an issuance of the second instruction to the second instruction execution unit when any of circuits positioning between the first plural staging latches or between the second plural staging latches is shared with circuits positioning between the plural second staging latches resulting from the execution of the second instruction by the second instruction execution unit when the first instruction execution unit executes the first instruction.   
     
     
         6 . The arithmetic processing device according to  claim 1 ,
 wherein the instruction control unit issues the first instruction to the first instruction execution unit and issues the second instruction to the second instruction execution unit such that the pipeline operation in the execution of the first instruction and the execution of the second instruction are partly overlapped.   
     
     
         7 . The arithmetic processing device according to  claim 1 ,
 wherein the instruction control unit issues the first instruction to the first instruction execution unit and issues the second instruction to the second instruction execution unit such that the pipeline operation or the multi-cycle operation in the execution of the first instruction and the execution of the second instruction are partly overlapped.   
     
     
         8 . A control method of an arithmetic processing device including a first instruction execution unit configured to include plural staging latches and execute a first instruction by a pipeline operation requiring only a single clock for transition of data between first plural staging latches including a staging latch at a final stage from among the plural staging latches, and a multi-cycle operation requiring plural clocks for transition of data between second plural staging latches positioning at a previous stage side than the first plural staging latches from among the plural staging latches; and a second instruction execution unit configured to execute a second instruction, the control method comprising:
 inputting the first instruction and the second instruction to an instruction control unit held by the arithmetic processing device; and   issuing the first instruction to the first instruction execution unit and issuing the second instruction to the second instruction execution unit by the instruction control unit such that the execution of the first instruction and the execution of the second instruction are partly overlapped.