US2015052312A1PendingUtilityA1

Protecting the footprint of memory transactions from victimization

Assignee: IBMPriority: Aug 15, 2013Filed: Sep 26, 2013Published: Feb 19, 2015
Est. expiryAug 15, 2033(~7 yrs left)· nominal 20-yr term from priority
G06F 12/0864G06F 12/0815G06F 9/467G06F 12/123G06F 12/0802
52
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of data processing in a data processing system having a processor core and a shared memory system including a cache memory, the method comprising:
 the cache memory tracking a transaction footprint including one or more cache lines accessed by one or more transactional memory access requests of a memory transaction undergoing execution by the processor core;   in response to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class of the cache memory:
 the cache memory forming a working set of ways in the congruence class containing one or more cache lines within the transaction footprint; and 
 the cache memory updating a replacement order of the cache lines in the congruence class, wherein the updating includes promoting at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced based on membership of the at least one cache line in the working set. 
   
     
     
         2 . The method of  claim 1 , wherein the updating includes updating the replacement order of the target cache line to most recently used (MRU). 
     
     
         3 . The method of  claim 2 , wherein the updating includes updating the replacement order of a most recently used cache line in the transaction footprint other than the target cache line to MRU−1. 
     
     
         4 . The method of  claim 1 , wherein the forming includes a directory of the cache memory forming the working set in response to a replacement order update message from transactional memory tracking logic within the cache memory. 
     
     
         5 . The method of  claim 1 , wherein:
 the transaction footprint includes a load footprint and a store footprint; and   the updating further comprises excluding from the promoting one of a set including the load footprint and the store footprint.   
     
     
         6 . The method of  claim 1 , and further comprising:
 in response to formation of an empty working set, updating the replacement order of the cache lines in the congruence class in accordance with a default replacement policy.

Join the waitlist — get patent alerts

Track US2015052312A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.