Semiconductor Device

Abstract

Provided is a user-friendly information processing system which is capable of maintaining latency within a fixed range and ensuring the expandability of a memory capacity at high speed and low cost. The information processing system, including an information processing device, a volatile memory, and nonvolatile memories, is configured. The information processing device, the volatile memory, and the nonvolatile memories are connected in series with one another to reduce the number of connection signals, thereby realizing speeding-up while maintaining the expandability of the memory capacity. The information processing device manages response time zones and time zones where responses overlap one another, and performs a correction operation on the latency, thereby realizing fast data transfer while maintaining the latency within the fixed range. The information processing device performs an error correction to improve the reliability when transferring the data of the nonvolatile memories to the volatile memory. The information processing system composed of a plurality of chips is configured as an information processing system/module in which the respective chips are arranged in layers, and wired together by a through via.

1 . A semiconductor device comprising:
 a first semiconductor device including:   a request transmitter circuit to issue an access request to an external section; and   a response receiver circuit to accept, from an external section, a response to the access request issued from the request transmitter circuit,   wherein a plurality of second semiconductor devices are connectable to the first semiconductor device, and   the first semiconductor device contains control target information indicating which semiconductor device is a target controlled by the first semiconductor device, the semiconductor device being of the plurality of second semiconductor devices which are targets controlled by the first semiconductor device.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the first semiconductor device includes a latency domain register, and   the control target information is stored in the latency domain register.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein the control target information is generated by the first semiconductor device when power is supplied to the first semiconductor device.   
     
     
         4 . The semiconductor device according to  claim 1 ,
 wherein the first semiconductor device is an information processing device,   each of the plurality of second semiconductor devices is a memory device, and   the control target information is updated when it is confirmed that the second semiconductor device is connected to the first semiconductor device.   
     
     
         5 . The semiconductor device according to  claim 1 ,
 wherein the first semiconductor device is an information processing device,   each of the plurality of second semiconductor devices is an information processing device, and   the control target information is updated when it is confirmed that the second semiconductor device is connected to the first semiconductor device.   
     
     
         6 . The semiconductor device according to  claim 1 ,
 wherein the first semiconductor device is an information processing device,   at least one of the plurality of second semiconductor devices is a memory device, and   the control target information is updated when it is confirmed that the second semiconductor device is connected to the first semiconductor device.