Receiver with enhanced isi mitigation

Abstract

A receiver integrated circuit is disclosed that includes a filter and a linear equalization circuit. The filter has an input to receive a signal symbols a main tap and a pre-cursor tap to reduces a pre-cursor ISI acting on the data symbols. The linear equalization circuit couples to the output and cooperates with the filter to further reduce ISI.

1 . A device having a signaling pad to receive an input signal, the device comprising:
 a transversal filter to receive the input signal from the signaling pad and generate an intermediate signal;   a circuit to equalize and sample the intermediate signal, and to thereby generate a digital output.   
     
     
         2 . The device of  claim 1  where the transversal filter includes at least one pre-cursor tap. 
     
     
         3 . The device of  claim 2  where the transversal filter is formed by at least one electrostatic discharge (ESD) structure. 
     
     
         4 . The device of  claim 2  where the transversal filter includes at least one post-cursor tap. 
     
     
         5 . The device of  claim 1  where the circuit includes a sampler circuit and a linear equalizer, the linear equalizer coupled to the transversal filter to receive the intermediate signal, the sampler circuit coupled to the linear equalizer to receive an output of the linear equalizer and generate the digital output therefrom. 
     
     
         6 . The device of  claim 5  where the circuit includes a sampling phase offset circuit, to shift a sampling phase used by the sampler circuit to sample at a data eye point less subject to precursor intersymbol interference (ISI). 
     
     
         7 . The device of  claim 5  where the circuit includes a sampling phase offset circuit, to shift a sampling phase used by the sampler circuit away from a point of maximum voltage margin to sample at a data eye point less subject to precursor intersymbol interference (ISI). 
     
     
         8 . The device of  claim 7  further comprising a decision feedback equalizer (DFE) circuit to adjust at least one of sampling or the intermediate signal to compensate for a previously-resolved digital symbol. 
     
     
         9 . The device of  claim 1  where the circuit includes a decision feedback equalizer (DFE) circuit to adjust sampling to compensate for a previously-resolved digital symbol. 
     
     
         10 . The device of  claim 1  where the transversal filter is formed by at least one electrostatic discharge (ESD) structure. 
     
     
         11 - 17 . (canceled) 
     
     
         18 . A receiver integrated circuit comprising:
 a filter to receive an external signal and responsively produce an intermediate signal, the filter including a main tap and at least one secondary tap to reduce intersymbol interference (ISI);   a sampler circuit to generate a sampled output in dependence on the intermediate signal; and   a decision-feedback equalization circuit coupled to the sampler circuit, the decision-feedback equalization circuit including at least one post-cursor equalization tap, such that the sampled output is equalized to reduce post-cursor ISI based on prior symbols from the sampled output.   
     
     
         19 . The receiver integrated circuit of  claim 18  and further including a linear equalizer to receive the intermediate signal and to generate an input for the sampler circuit. 
     
     
         20 . The receiver integrated circuit of  claim 19  where the linear equalizer is to equalize the intermediate signal to compensate for post-cursor ISI. 
     
     
         21 . The receiver integrated circuit of  claim 18  where the receiver integrated circuit further comprises phase adjustment circuitry to receive and adjust a timing signal for phase based on a measure representing pre-cursor ISI, to generate a sampler circuit timing signal. 
     
     
         22 . A method of operation in a receiver integrated circuit, the receiver integrated circuit to receive an input signal, the method comprising:
 filtering the input signal using a filter at least two taps, including a main tap and a secondary tap, to generate an intermediate signal; and   using a circuit to equalize and sample the intermediate signal to generate a stream of digital symbols.   
     
     
         23 . The method of  claim 22  where the circuit includes a linear equalizer to equalize the intermediate signal to produce an output, and a sampler circuit to sample the output of the linear equalizer to produce the stream of digital symbols. 
     
     
         24 . The method of  claim 23  where:
 sampling is performed in response to a timing signal representing a sampling phase; and 
 the method further comprises adjusting the sampling phase based on a measure of pre-cursor ISI, to force a sampling instant displaced from maximum voltage margin relative to a data threshold. 
 
     
     
         25 . The method of  claim 23  where the receiver integrated circuit includes a decision feedback equalization (DFE) circuit and where:
 sampling includes equalizing an output of the linear equalizer in dependence upon a binary state of a prior symbol in the stream of digital symbols. 
 
     
     
         26 . The method of  claim 22  where filtering comprises:
 filtering a current data symbol based on electrical characteristics exhibited by a plurality of distributed LC circuit elements. 
 
     
     
         27 . The method of  claim 26  where the input signal is received via a signal pad and where the plurality of distributed LC circuit elements provide electrostatic discharge (ESD) protection to the signal pad. 
     
     
         28 - 59 . (canceled)