US2015049543A1PendingUtilityA1

Phase change memory word line driver

47
Assignee: CONVERSANT INTELLECTUAL PROPERTY MAN INCPriority: Jun 23, 2010Filed: Nov 2, 2014Published: Feb 19, 2015
Est. expiryJun 23, 2030(~3.9 yrs left)· nominal 20-yr term from priority
Inventors:Hong Beom Pyeon
G11C 13/0069G11C 13/0004G11C 8/14G11C 13/0028G11C 8/08G11C 2013/0071G11C 13/0038G11C 13/004
47
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Claims

Abstract

A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for improving word line response comprising:
 generating a variable substrate bias;   applying the variable substrate bias to a word line driver in a selected block of a memory during a write operation;   applying a bias of Vss to word line drivers in the remaining blocks of the memory; and   modifying a variable substrate bias of the word line driver depending on a trim value.   
     
     
         2 . The method of  claim 1  wherein generating the variable substrate bias includes shunting at least one resistor based on the trim value, each resistor being in series with a bias resistor and dividing a voltage. 
     
     
         3 . The method of  claim 1  wherein the trim value depends on a number of a plurality of memory cells in communication with the word line. 
     
     
         4 . The method of  claim 1  wherein the trim value depends on an address of a plurality of memory cells in communication with the word line. 
     
     
         5 . The method of  claim 1  wherein the trim value depends on an array configuration of a memory comprising a plurality of memory cells in communication with the word line. 
     
     
         6 . The method of  claim 1 , wherein the variable substrate bias voltage is greater than or equal to 0.1 volts and less than or equal to 0.69 volts. 
     
     
         7 . The method of  claim 1 , wherein the trim value is user programmable. 
     
     
         8 . The method of  claim 1 , further comprising:
 applying a bias of Vss to the word line driver in the selected block of the memory during a read operation.   
     
     
         9 . An adaptable word line driver comprising:
 a word line driver in communication with a plurality of memory cells in a memory, the word line driver including a transistor with a variable substrate bias voltage, a source of the transistor being in communication with a ground potential and a drain of the transistor in communication with a word line, the transistor being formed in a P-well and being in communication with the variable substrate bias voltage; and   a variable substrate bias voltage generator including at least one resistor in series with a bias resistor, each resistor being in parallel with a shunting transistor controlled by a trim value, the at least one resistor and the bias resistor dividing a bias voltage to produce the variable substrate bias voltage.   
     
     
         10 . The adaptable word line driver of  claim 11  wherein the variable substrate bias voltage is greater than or equal to 0.1 volts and less than or equal to 0.69 volts. 
     
     
         11 . The adaptable word line driver of  claim 9  wherein the trim value is user programmable. 
     
     
         12 . The adaptable word line driver of  claim 9  wherein the trim value depends on a number of the plurality of memory cells to be programmed. 
     
     
         13 . The adaptable word line driver of  claim 9  wherein the trim value depends on an address of the plurality of memory cells to be programmed. 
     
     
         14 . The adaptable word line driver of  claim 9  wherein the trim value depends on an array configuration of the memory. 
     
     
         15 . A memory system comprising:
 a plurality of arrays of a memory, each array including a plurality of memory cells in communication with at least one word line driver, the at least one word line driver of each array being formed in a P-well and being in communication with a variable substrate bias voltage;   a variable substrate bias voltage generator including at least one resistor in series with a bias resistor, each resistor being in parallel with a shunting transistor controlled by a trim value, the at least one resistor and the bias resistor dividing a bias voltage to produce the variable substrate bias voltage; and   an address decoder selecting one of the plurality of arrays, the address decoder enabling communication with the variable substrate bias voltage generator and the selected one of the plurality of arrays.   
     
     
         16 . The system of  claim 15  wherein the variable substrate bias voltage is greater than or equal to 0.1 volts and less than or equal to 0.69 volts. 
     
     
         17 . The system of  claim 15  wherein the trim value is user programmable. 
     
     
         18 . The system of  claim 15  wherein the trim value depends on a number of the plurality of memory cells to be programmed. 
     
     
         19 . The system of  claim 15  wherein the trim value depends on an address of the plurality of memory cells to be programmed. 
     
     
         20 . The system of  claim 15  wherein the trim value depends on an array configuration of the memory. 
     
     
         21 . The system of  claim 15  wherein the memory is a phase change memory.

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