System on chip for reducing wake-up time, method of operating same, and computer system including same

Abstract

A system on chip (SoC) includes an internal read-only memory (ROM) configured to store a first boot loader; a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.

1 . A method of operating a system on chip (SoC), the method comprising:
 executing a first boot loader stored in an internal read-only memory (ROM) based on a reset signal;   selecting one of non-volatile memories as a booting device using the first boot loader;   loading a second boot loader from the booting device into a first internal static random access memory (SRAM) and loading a third boot loader from the booting device into a second internal SRAM; and   loading an operating system (OS) from the booting device into a main memory as the second boot loader is executed.   
     
     
         2 . The method of  claim 1 , further comprising:
 executing the second boot loader, wherein the second boot loader is executed after the third boot loader loaded into the second internal SRAM passes integrity checking.   
     
     
         3 . The method of  claim 1 , wherein the non-volatile memories are flash-based memories. 
     
     
         4 . The method of  claim 1 , further comprising:
 causing the SoC to enter a power-down mode;   cutting off a power supply to the internal ROM and the first internal SRAM during the power-down mode; and   continuing supplying power to the second internal SRAM in the power-down mode.   
     
     
         5 . The method of  claim 4 , further comprising:
 executing the first boot loader based on a wake-up interrupt signal;   executing, using the first boot loader, the third boot loader stored in the second internal SRAM; and   jumping to the OS loaded into the main memory, using the third boot loader.   
     
     
         6 . The method of  claim 1 , further comprising:
 performing integrity checking on at least one of the second boot loader, the third boot loader, and the OS.   
     
     
         7 . The method of  claim 1 , wherein the reset signal is one of a hardware reset signal, a watchdog reset signal, and a software reset signal. 
     
     
         8 . A system on chip (SoC) comprising:
 an internal read-only memory (ROM) configured to store a first boot loader;   a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader;   a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and   a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader.   
     
     
         9 . The SoC of  claim 8 , wherein the first internal SRAM and the second internal SRAM are respectively implemented in different power domains, the SoC being configured to control the different power domains independently with respect to one another. 
     
     
         10 . The SoC of  claim 8 , further comprising:
 a power management unit (PMU) configured to cut off a power supply to the internal ROM, the first internal SRAM, and the DRAM controller and to continue supplying power to the second internal SRAM after the SoC enters a power-down mode.   
     
     
         11 . The SoC of  claim 10 , wherein the PMU resumes supplying power to the internal ROM, the first internal SRAM, and the DRAM controller based on a wake-up interrupt signal; the first boot loader is executed based on the wake-up interrupt signal; and the third boot loader jumps to the OS loaded into the DRAM, the first boot loader being executed by the first boot loader. 
     
     
         12 - 14 . (canceled) 
     
     
         15 . A computer system comprising:
 a system on chip (SoC);   a booting device connected to the SoC; and   a dynamic random access memory (DRAM) connected to the SoC,   wherein the SoC includes,
 an internal read-only memory (ROM) configured to store a first boot loader; 
 a first internal static random access memory (SRAM) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; 
 a second internal SRAM configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and 
 a dynamic random access memory (DRAM) controller configured to load an operating system (OS) from the booting device into a DRAM according to control of the second boot loader. 
   
     
     
         16 . The computer system of  claim 15 , wherein the first internal SRAM and the second internal SRAM are respectively implemented in different power, the SoC being configured to control the different power domains independently with respect to one another. 
     
     
         17 . The computer system of  claim 15 , further comprising a power management unit (PMU) configured to cut off a power supply to the internal ROM, the first internal SRAM, and the DRAM controller and to continue supplying power to the second internal SRAM after the SoC enters a power-down mode. 
     
     
         18 . The computer system of  claim 17 , wherein the PMU resumes supplying power supply to the internal ROM, the first internal SRAM, and the DRAM controller based on a wake-up interrupt signal; the first boot loader is executed based on the wake-up interrupt signal; and the third boot loader jumps to the OS loaded into the DRAM, the first boot loader being executed by the first boot loader. 
     
     
         19 . The computer system of  claim 15 , further comprising:
 a power supply control device configured to cut off a power supply to the booting device when the SoC is in a power-down mode and to resume the supplying power to the booting device when the SoC wakes up.   
     
     
         20 . The computer system of  claim 15 , wherein the computer system is at least one of a smart phone, a tablet personal computer, a wearable computer, and a mobile internet device. 
     
     
         21 - 24 . (canceled)