Semiconductor fin on local oxide

Abstract

A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

What is claimed is: 
     
         1 . A method of forming a semiconductor structure comprising:
 providing a semiconductor substrate including a first epitaxial semiconductor layer comprising a first single crystalline semiconductor material;   forming a second epitaxial semiconductor layer comprising a second single crystalline semiconductor material in epitaxial alignment with, and having a different composition from, said first single crystalline semiconductor material on said first epitaxial semiconductor layer;   forming a semiconductor fin by patterning said second epitaxial semiconductor material layer;   forming an oxygen-impermeable spacer on sidewalls of said semiconductor fin; and   forming a semiconductor oxide portion by oxidizing at least portions of said first epitaxial semiconductor layer, wherein a remaining portion of said semiconductor fin is vertically spaced from an unoxidized semiconductor material portion of said semiconductor substrate by said semiconductor oxide portion.   
     
     
         2 . The method of  claim 1 , wherein said unoxidized semiconductor material portion of said semiconductor substrate comprises an unoxidized portion of said first epitaxial semiconductor layer. 
     
     
         3 . The method of  claim 1 , further comprising oxidizing a lower portion of said semiconductor fin, wherein said oxidized lower portion of said semiconductor fin is incorporated into said semiconductor oxide portion. 
     
     
         4 . The method of  claim 1 , wherein said first single crystalline semiconductor material has a greater oxidation rate than said second single crystalline semiconductor material. 
     
     
         5 . The method of  claim 4 , wherein said first single crystalline semiconductor material comprises a silicon germanium alloy, and said second single crystalline semiconductor material comprises silicon. 
     
     
         6 . The method of  claim 4 , wherein said first single crystalline semiconductor material comprises germanium or a silicon germanium alloy, and said second single crystalline semiconductor material comprises another silicon germanium alloy having a greater atomic concentration of silicon than said first single crystalline semiconductor material. 
     
     
         7 . The method of  claim 1 , further comprising recessing a top surface of said first epitaxial semiconductor layer relative to a bottom surface of said oxygen-impermeable spacer prior to said forming of said semiconductor oxide portion. 
     
     
         8 . The method of  claim 7 , wherein a depth of said recessing does not exceed a thickness of said first epitaxial semiconductor layer. 
     
     
         9 . The method of  claim 7 , further comprising removing portions of said first epitaxial semiconductor layer underneath said oxygen impermeable spacer by an isotropic etch prior to said forming of said semiconductor oxide portion. 
     
     
         10 . The method of  claim 1 , wherein said semiconductor substrate is formed by:
 providing a single crystalline semiconductor substrate including a third single crystalline semiconductor material that is different from said first single crystalline semiconductor material; and   epitaxially depositing said first epitaxial semiconductor layer on said single crystalline semiconductor substrate.   
     
     
         11 . The method of  claim 10 , wherein an entirety of said first epitaxial semiconductor layer and an upper portion of said single crystalline semiconductor substrate are oxidized to form said semiconductor oxide portion. 
     
     
         12 . The method of  claim 1 , wherein said first epitaxial semiconductor layer extends throughout an entirety of said semiconductor substrate. 
     
     
         13 . The method of  claim 1 , wherein said forming of said semiconductor fin comprises:
 forming a patterned etch mask layer over said second epitaxial semiconductor layer; and   transferring a pattern in said patterned etch mask layer by an anisotropic etch through said second epitaxial semiconductor layer employing said first epitaxial semiconductor layer as an etch stop layer, wherein said semiconductor fin including a remaining portion of said second epitaxial semiconductor material layer is formed by said anisotropic etch.   
     
     
         14 . The method of  claim 13 , further comprising forming a dielectric layer on said second epitaxial semiconductor layer and forming an oxygen-impermeable layer on said dielectric layer prior to said forming of said pattered etch mask layer, wherein said transferring said pattern is through said dielectric layer, said oxygen-impermeable layer, and said second epitaxial semiconductor layer. 
     
     
         15 . The method of  claim 14 , further comprising removing said oxygen-impermeable spacer and remaining portions of said oxygen-impermeable layer. 
     
     
         16 . The method of  claim 15 , further comprising forming a vertical stack of a gate dielectric and a gate electrode over a portion of semiconductor fin. 
     
     
         17 . The method of  claim 16 , wherein said forming said vertical stack of said gate dielectric and said gate electrode comprises:
 depositing a stack of a gate dielectric layer and a conductive material layer; and   pattering said stack of said gate dielectric layer and said conductive material layer by a combination of lithographic methods and at least one anisotropic etch.   
     
     
         18 . The method of  claim 16 , further comprising forming at least one gate spacer around said vertical stack of said gate dielectric and said gate electrode. 
     
     
         19 . The method of  claim 18 , further comprising forming a source region and a drain region on opposite sides of said gate spacer.