Counting circuit, delay value quantization circuit, and latency control circuit

Abstract

A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

1 . A counting circuit comprising:
 a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal;   a counting unit configured to count the divided clock signal; and   a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.   
     
     
         2 . The counting circuit of  claim 1 , wherein, if the preset division ratio is 1/N, the counting control unit sets the enable period to a period N times longer than an enable period when the division ratio is 1. 
     
     
         3 . The counting circuit of  claim 2 , wherein the counting control unit generates an enable signal to enable the counting unit, and
 if the preset division ratio is 1/N, a period during which the enable signal is activated is set N times longer than a period during which the enable signal is activated when the division ratio is 1.   
     
     
         4 . The counting circuit of  claim 2 , wherein a counting result of the counting unit has the same value regardless of the preset division ratio. 
     
     
         5 - 9 . (canceled) 
     
     
         10 . A latency control circuit comprising:
 a clock division unit configured to divide a reference clock signal and generate a divided clock signal;   a replica delay unit having a delay value corresponding to a path through which an input signal passes in an integrated circuit;   a counting control unit configured to control the replica delay unit to delay a start signal, which is activated in response to the input signal, a preset number of times, and to activate an end signal if an output signal of the replica delay unit is activated for the preset number of times;   a counting unit configured to count the divided clock signal from an activation time point of the start signal to an activation time point of the end signal, and to generate a path information corresponding to the delay value of the path through which the input signal passes in the integrated circuit;   a delay information generation unit configured to generate a delay information indicating a value for delaying the input signal, using a latency information of the input signal and the path information; and   a delay unit configured to delay the input signal by the delay information.   
     
     
         11 . The latency control circuit of  claim 10 , wherein the path information comprises information obtained by quantizing the delay value of the replica delay unit based on the divided clock signal. 
     
     
         12 . The latency control circuit of  claim 10 , wherein the preset number of times is decided based on a division ratio of the clock division unit. 
     
     
         13 . The latency control circuit of  claim 12 , wherein, when the division ratio is 1/N, the preset number of times is set to N. 
     
     
         14 . The latency control circuit of  claim 10 , wherein the delay information generation unit generates the delay information by subtracting a value of the path information from a value of the latency information.