Semiconductor memory device

Abstract

A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.

What is claimed is: 
     
         1 . A device comprising:
 a semiconductor substrate;   first and second wiring layers formed in the semiconductor substrate;   a first level wiring formed over the semiconductor substrate;   third and forth wiring layers formed as the first level wiring;   a first transistor including a first pillar element that comprises a first diffusion layer at one end thereof and a second diffusion layer at the other end thereof, and a first gate electrode that surrounds a part of the first pillar element, the first transistor being coupled to the first wiring layer at the first diffusion layer thereof and coupled to the third wiring layer at the second diffusion layer thereof, receiving a control signal at the first gate electrode thereof, the first transistor being rendered conductive when the control signal changes to a first logic level, and the first transistor being rendered nonconductive when the control signal changes to a second logic level, and   a second transistor including a second pillar element that comprises a third diffusion layer at one end thereof and a fourth diffusion layer at the other end thereof, and a second gate electrode that surrounds a part of the second pillar element, the second transistor being coupled to the second wiring layer at the third diffusion layer thereof and coupled to the fourth wiring layer at the fourth diffusion layer thereof, the second transistor remaining conductive during a period of time when the device operates.   
     
     
         2 . The device as claimed in  claim 1 , wherein the second gate electrode of the second transistor is supplied with a first power supply voltage that is substantially constant during the period of time. 
     
     
         3 . The device as claimed in  claim 1 , wherein the second pillar element of the second transistor includes a diffusion portion electrically connecting the third diffusion layer thereof to the fourth diffusion layer thereof. 
     
     
         4 . The device as claimed in  claim 1 , wherein the first pillar element of the first transistor is substantially equal in size to the second pillar element of the second transistor. 
     
     
         5 . The device as claimed in  claim 1 , wherein the first wiring layer is coupled to the second wiring layer. 
     
     
         6 . The device as claimed in  claim 1 , wherein the third wiring layer is coupled to the fourth wiring layer. 
     
     
         7 . A device comprising:
 a semiconductor substrate;   first and second bit lines formed in the semiconductor substrate;   first and second transistors each including a first pillar element that comprises a first diffusion layer at one end thereof and a second diffusion layer at the other end thereof, and a gate electrode that surrounds a part of the first pillar element, the first transistor being coupled to the first bit line at the first diffusion layer thereof, the second transistor being coupled to the second bit line at the first diffusion layer thereof; and   a first conductive path connecting the gate electrode of the first transistor to the second diffusion layer of the second transistor.   
     
     
         8 . The device as claimed in  claim 7 , wherein the gate electrode of the second transistor is supplied with a first voltage that is substantially constant independently from voltage levels of the first and the second bit lines. 
     
     
         9 . The device as claimed in  claim 7 , wherein the pillar element of the second transistor includes a diffusion portion electrically connecting the first diffusion layer thereof to the second diffusion layer thereof. 
     
     
         10 . The device as claimed in  claim 7 , further comprising:
 a first insulating layer formed over the semiconductor to cover the first and the second transistors, and   a first level wiring layer formed above the first insulating layer, and wherein the first conductive path includes a first wiring layer formed as a first level wiring.   
     
     
         11 . The device as claimed in  claim 10 , further comprising a second pillar element formed above the first bit line being electrically disconnected from the first bit line, and wherein the first conductive path includes a ring conductive layer surrounding the second pillar element and in contact with the gate electrode of the first transistor. 
     
     
         12 . The device as claimed in  claim 10 , further comprising:
 a third transistor including a second pillar element that comprises a third diffusion layer at one end thereof and a fourth diffusion layer at the other end thereof, and a gate electrode that surrounds a part of the third pillar element, the third transistor being coupled to the second bit line at the third diffusion layer thereof,   a second wiring layer formed as the first level wiring layer and coupled to both the second diffusion layer of the first transistor and the forth diffusion layer of the third transistor.   
     
     
         13 . The device as claimed in  claim 12 , further comprising:
 a third wiring layer formed in the semiconductor substrate,   fourth and fifth transistors each including a third pillar element that comprises a fifth diffusion layer at one end thereof and a sixth diffusion layer at the other end thereof, and a gate electrode that surrounds a part of the third pillar element, the fourth and fifth transistors being coupled to the third wiring layer at the fifth diffusion layer thereof, the fourth transistor being coupled to the second wiring layer at the sixth diffusion layer thereof, and   a fourth wiring layer formed as the first level wiring layer and insulated from the first and the second wiring layer, the fourth wiring layer being coupled to the sixth diffusion layer of the fifth transistor to supply the fifth transistor with a second voltage that is substantially a power supply voltage.   
     
     
         14 . The device as claimed in  claim 13 , wherein the gate electrode of the fifth transistor is supplied with the first voltage. 
     
     
         15 . The device as claimed in  claim 7 , further comprising;
 a third transistor including a second pillar element that comprises a third diffusion layer at one end thereof and a fourth diffusion layer at the other end thereof, and a gate electrode that surrounds a part of the third pillar element, the third transistor being coupled to the second bit line at the third diffusion layer thereof,   fourth and fifth transistors each including a third pillar element that comprises a fifth diffusion layer at one end thereof and a sixth diffusion layer at the other end thereof, and a gate electrode that surrounds a part of the third pillar element, the fourth transistor being coupled to the first bit line at the fifth diffusion layer thereof, and the fifth transistor being coupled to the second bit line at the fifth diffusion layer thereof, and wherein the first, the second, and the third transistors are of a first conductivity type and the fourth and fifth transistors are of a second conductivity type different from the first conductivity type.   
     
     
         16 . The device as claimed in  claim 15 , wherein the first, the third, the fourth and the fifth transistors cooperate with each other to amplify a voltage difference between the first and the second bit lines.