Multi-Channel Scalable EEG Acquisition System on a Chip with Integrated Patient Specific Seizure Classification and Recording Processor

Abstract

An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

What is claimed is: 
     
         1 . An integrated circuit chip for EEG monitoring, comprising:
 an Analog Front End cell, the Analog Front End cell comprising:
 an amplifier cell in communication with an EEG electrode; 
 an ASPU cell in communication with the amplifier cell; and 
   a Classification Processor comprising:
 a DBE Channel Controller cell; 
 a Feature Extraction Engine Processor cell, the Feature Extraction Engine Processor cell in communication with the DBE Channel Controller cell and the Analog Front End cell; and 
 a Classification Engine cell in communication with the Feature Extraction Engine Processor cell and the DBE Channel Controller cell, 
   wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure.   
     
     
         2 . The integrated circuit chip of  claim 1  wherein the amplifier cell in communication with the electrode is a CS-CCIA cell. 
     
     
         3 . The integrated circuit chip of  claim 1  wherein the amplifier cell in communication with the electrode is an autozeroing amplifier circuit cell. 
     
     
         4 . The integrated circuit chip of  claim 1  wherein the Feature Extraction Engine Processor cell comprises:
 a plurality of bandpass filter cells, each bandpass filter cell in communication with the ASPU cell; and 
 a plurality of integrator cells, each integrator cell in communication with a respective one of the plurality of bandpass filter cells; 
 wherein a signal from the ASPU cell of an Analog Front End is filtered by a plurality of bandpass filters to form a plurality of sub-bands, and 
 wherein each of the sub-bands is integrated by a respective one of the plurality of integrator cells to determine the energy of the sub-band. 
 
     
     
         5 . The integrated circuit chip of  claim 4  wherein the Feature Extraction Engine Processor cell further comprises:
 a decimation filter cell in communication between the ASPU cell and the plurality of bandpass filter cells, 
 and wherein a signal from the ASPU cell of an Analog Front End is decimated by the decimation cell prior to being filtered by the plurality of bandpass filter cells. 
 
     
     
         6 . The integrated circuit chip of  claim 4  wherein the integrated sub-bands are aggregated to form a feature vector. 
     
     
         7 . The integrated circuit chip of  claim 6  wherein Classification Engine cell designates the signal received from the electrode as a seizure condition or a non-seizure condition in response to the feature vector. 
     
     
         8 . The integrated circuit chip of  claim 1  further comprising an analog to digital converter cell in communication with the ASPU cell and the Feature extraction cell. 
     
     
         9 . The integrated circuit chip of  claim 8  wherein the analog to digital converter cell in communication with the ASPU cell and the Feature extraction cell is a SAR ADC. 
     
     
         10 . The integrated circuit chip of  claim 7  wherein the Classification Engine comprises an SVM and the SVM designates the signal, received from the electrode, as seizure or non-seizure in response to the feature vector, by determining on which side of a hyperplane in feature hyperspace the feature vector lies. 
     
     
         11 . The integrated circuit chip of  claim 1 :
 wherein the Analog Front End cell is a plurality of Analog Front End cells,   wherein the Feature Extraction Engine cell is a plurality of Feature Extraction Engine cells, and   wherein each Feature Extraction Engine cell is in communication with a respective one of the Analog Front End cells.   
     
     
         12 . The integrated circuit chip of  claim 11  further comprising:
 a multiplexer cell in communication with the plurality of Analog Front End cells; and 
 an ADC cell in communication with the multiplexer cell and the plurality of Feature Extraction Engine processor cells. 
 
     
     
         13 . The integrated circuit chip of  claim 12 , where the ADC cell is an SAR cell. 
     
     
         14 . The integrated circuit chip of  claim 1  wherein the DBE Channel controller comprises:
 a channel gain control line and a channel bandwidth control line in communication with an Analog Front End cell. 
 
     
     
         15 . The integrated circuit chip of  claim 12  wherein the DBE Channel Controller comprises:
 a channel gain control line, a channel bandwidth control line, and a channel number select in communication with the AFE Channel Controllers and a channel select control line in communication with the multiplexer cell, 
 wherein the DBE Channel Controller is in communication with an external data interface, and 
 wherein the DBE Channel Controller selects the number of channel to be used in response to receiving the number of channels from the external data interface and setting the respective AFE Channel Controller on or off. 
 
     
     
         16 . The integrated circuit chip of  claim 4  each bandpass filter comprises:
 a plurality of LUTs, each LUT having a plurality of inputs and having an output, 
 a plurality of bit shift registers, each bit shift register having an input in communication with the ASPU and an output in communication with a respective input of the LUT; 
 a summer having a first input in communication with the output of the LUT and having a second input and an output; and 
 a register having an input in communication with the output of the summer and having an output in communication with the second input of the summer; 
 wherein the output of the bandpass filter is the output of the register. 
 
     
     
         17 . The integrated circuit chip of  claim 16  wherein the LUT is a distributed quad-LUT. 
     
     
         18 . The integrated circuit chip of  claim 2  wherein the CS-CCIA comprises:
 an input-chopped switch having an input in communication with the electrode and having an output; 
 a low noise amplifier having an input in communication with the output of the input-chopped switch and an first output connected to an input of the ASPU and having a second output; 
 an Impedance Boosting Loop comprising a IBL chopper switch having an input in communication with the low noise amplifier output and an output in communication with the low noise amplifier input; 
 a DC Servo Loop comprising:
 a DSL amplifier having an input in communication with the output of the low noise amplifier; 
 a DSL chopper switch having an input in communication with the output of the DSL amplifier and a output in communication with the input of the low noise amplifier; and 
 
 an Offset Cancellation Loop comprising:
 an OCL amplifier having an input in communication with the second output of the low noise amplifier and having an output; 
 an OCL chopped switch having an input in communication with the output of the OCL amplifier and having an output; 
 a high pass filter having an input in communication with the output of the OCL chopped switch and having an output; and 
 an gain chopped switch having an input in communication with the output of the high pass filter and having an output in communication with the input of the low noise amplifier. 
 
 
     
     
         19 . The integrated circuit chip of  claim 3  wherein the autozeroing amplifier circuit cell comprises:
 an auto zero amplifier having an input in communication with the electrode and having an output; 
 a low noise amplifier having an input in communication with the output of the autozero amplifier and an first output connected to an input of the ASPU and having a second output; 
 an Impedance Boosting Loop comprising a IBL chopper switch having an input in communication with the low noise amplifier output and an output in communication with the low noise amplifier input; 
 a DC Servo Loop comprising:
 a DSL amplifier having an input in communication with the output of the low noise amplifier; 
 a DSL chopper switch having an input in communication with the output of the DSL amplifier and a output in communication with the input of the low noise amplifier; and 
 
 an Offset Cancellation Loop comprising:
 an OCL amplifier having an input in communication with the second output of the low noise amplifier and having an output; 
 an OCL chopped switch having an input in communication with the output of the OCL amplifier and having an output; 
 a high pass filter having an input in communication with the output of the OCL chopped switch and having an output; and 
 an gain chopped switch having an input in communication with the output of the high pass filter and having an output in communication with the input of the low noise amplifier. 
 
 
     
     
         20 . The integrated circuit chip of  claim 1  further comprising:
 a bus; 
 an SRAM in communication with the bus; 
 an external memory interface in communication with the bus; and 
 an external data interface in communication with the bus; 
 wherein the bus is in communication with the Classification Processor. 
 
     
     
         21 . A method for monitoring an EEG using an integrated circuit chip comprising the steps of:
 amplifying a signal from an EEG electrode to generate an amplified EEG signal;   adapting the gain of the amplified EEG signal using an ASPU;   digitizing the adapted gain signal using an analog to digital converter;   extracting a feature vector from the digitized adapted gain signal using a feature extraction engine; and   designating the feature vector as seizure or non-seizure using a classification engine.   
     
     
         22 . The method of  claim 21  wherein the step of adapting the gain of the amplified EEG signal occurs in real-time. 
     
     
         23 . The method of  claim 21  the step of extracting a feature vector comprises the steps of:
 dividing the digitized adapted gain signal into a plurality of sub-bands; 
 integrating each sub-band to calculate the energy within each sub-band; and 
 aggregating each integrated sub-band to generate a feature vector. 
 
     
     
         24 . The method of  claim 21  wherein the step of designating the feature vector as seizure or non-seizure comprises the steps of:
 generating, in response to patient data, a hyperplane separating a seizure region of feature hyperspace from a non-seizure region of feature hyper space; and 
 determining in which region of feature hyperspace the feature vector exists. 
 
     
     
         25 . The method of  claim 23  wherein the step of dividing the digitized adapted gain signal into a plurality of sub-bands utilizes a LUT. 
     
     
         26 . A CS-CCIA comprising:
 an input-chopped switch having an input in communication with a signal source and having an output;   a low noise amplifier having an input in communication with the output of the input-chopped switch and an first output connected to an input of the ASPU and having a second output;   an Impedance Boosting Loop comprising a IBL chopper switch having an input in communication with the low noise amplifier output and an output in communication with the low noise amplifier input;   a DC Servo Loop comprising:
 a DSL amplifier having an input in communication with the output of the low noise amplifier; 
 a DSL chopper switch having an input in communication with the output of the DSL amplifier and a output in communication with the input of the low noise amplifier; and 
   an Offset Cancellation Loop comprising:
 an OCL amplifier having an input in communication with the second output of the low noise amplifier and having an output; 
 an OCL chopped switch having an input in communication with the output of the OCL amplifier and having an output; 
 a high pass filter having an input in communication with the output of the OCL chopped switch and having an output; and 
 an gain chopped switch having an input in communication with the output of the high pass filter and having an output in communication with the input of the low noise amplifier. 
   
     
     
         27 . The CS-CCIA of  claim 26  wherein the Impedance Boosting Loop comprises a IBL chopper switch having an input in communication with the low noise amplifier output and an output in communication with the low noise amplifier input. 
     
     
         28 . The CS-CCIA of  claim 26  wherein the DC Servo Loop comprises:
 a DSL amplifier having an input in communication with the output of the low noise amplifier; 
 a DSL chopper switch having an input in communication with the output of the DSL amplifier and a output in communication with the input of the low noise amplifier. 
 
     
     
         29 . The CS-CCIA of  claim 26  wherein the Offset Cancellation Loop comprises:
 an OCL amplifier having an input in communication with the second output of the low noise amplifier and having an output; 
 an OCL chopped switch having an input in communication with the output of the OCL amplifier and having an output; 
 a high pass filter having an input in communication with the output of the OCL chopped switch and having an output; and 
 an gain chopped switch having an input in communication with the output of the high pass filter and having an output in communication with the input of the low noise amplifier. 
 
     
     
         30 . An autozero amplifier circuit cell comprising:
 an autozero amplifier cell having an input in communication with a signal source and having an output;   a low noise amplifier having an input in communication with the output of the autozero amplifier cell, a first output and a second output;   an Impedance Boosting Loop comprising a IBL chopper switch having an input in communication with the low noise amplifier output and an output in communication with the low noise amplifier input;   a DC Servo Loop comprising:
 a DSL amplifier having an input in communication with the output of the low noise amplifier; 
 a DSL chopper switch having an input in communication with the output of the DSL amplifier and a output in communication with the input of the low noise amplifier; and 
   an Offset Cancellation Loop comprising:
 an OCL amplifier having an input in communication with the second output of the low noise amplifier and having an output; 
 an OCL chopped switch having an input in communication with the output of the OCL amplifier and having an output; 
 a high pass filter having an input in communication with the output of the OCL chopped switch and having an output; and 
 an gain chopped switch having an input in communication with the output of the high pass filter and having an output in communication with the input of the low noise amplifier. 
   
     
     
         31 . The autozero amplifier circuit cell of  claim 30  wherein the Impedance Boosting Loop comprises a IBL chopper switch having an input in communication with the low noise amplifier output and an output in communication with the low noise amplifier input. 
     
     
         32 . The autozero amplifier circuit cell of  claim 30  wherein the DC Servo Loop comprises:
 a DSL amplifier having an input in communication with the output of the low noise amplifier; 
 a DSL chopper switch having an input in communication with the output of the DSL amplifier and a output in communication with the input of the low noise amplifier. 
 
     
     
         33 . The autozero amplifier circuit cell of  claim 30  wherein the Offset Cancellation Loop comprises:
 an OCL amplifier having an input in communication with the second output of the low noise amplifier and having an output; 
 an OCL chopped switch having an input in communication with the output of the OCL amplifier and having an output; 
 a high pass filter having an input in communication with the output of the OCL chopped switch and having an output; and 
 an gain chopped switch having an input in communication with the output of the high pass filter and having an output in communication with the input of the low noise amplifier. 
 
     
     
         34 . A bandpass filter comprising:
 a plurality of LUTs, each LUT having a plurality of inputs and having an output,   a plurality of bit shift registers, each bit shift register having an input in communication with a digital signal source and an output in communication with a respective input of the plurality of inputs of the LUT;   a summer having a first input in communication with the output of the LUT and having a second input and an output; and   a register having an input in communication with the output of the summer and having an output in communication with the second input of the summer;   wherein the output of the bandpass filter is the output of the register.   
     
     
         35 . The bandpass filter of  claim 34  wherein each lut is a distributed quad-LUT.