Methods of forming memory cells, memory cells, and semiconductor devices

Abstract

A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

1 . A method of forming a memory cell, comprising:
 selectively removing material from a substrate to form a body having a fin-like structure;   forming a gate structure wrapping around multiple surfaces of a portion of the body;   introducing dopant of a first conductivity type into the body at a position underlying and approximately aligned with an edge of the gate structure to form a first doped region;   forming at least one of nano-particles and nano-inclusions in the first doped region; and   introducing dopant of a second conductivity type into the substrate to form each of a second doped region comprising at least one of a source and drain region and a third doped region comprising at least one of an opposing source and an opposing drain region, the first doped region adjacent the third doped region and separated from the second doped region by an undoped region.   
     
     
         2 . The method of  claim 1 , wherein selectively removing material from a substrate to form a body having a fin-like structure comprises etching a silicon material of a silicon-on-insulator substrate comprising a base silicon material, a buried oxide material over the base silicon material, and the silicon material over the buried oxide material. 
     
     
         3 . The method of  claim 1 , wherein forming a gate structure wrapping around multiple surfaces of a portion of the body comprises:
 forming an insulating material having a high dielectric constant on the substrate;   depositing a conductive material over the insulating material; and   selectively removing portions of the conductive material and the insulating material.   
     
     
         4 . The method of  claim 3 , wherein forming an insulating material having a high dielectric constant comprises forming at least one of hafnium oxide, nitrided hafnium oxide, aluminum-doped hafnium oxide, aluminum oxide, zirconium oxide, tantalum pentoxide, lanthanum oxide, titanium oxide, and yttrium oxide. 
     
     
         5 . The method of  claim 3 , wherein selectively removing portions of the conductive material and the insulating material comprises etching the insulating material such that a thickness of the insulating material on a top surface of the body is greater than a thickness of the insulating material on sidewalls of the body. 
     
     
         6 . The method of  claim 1 , wherein introducing a dopant of a first conductivity type comprises implanting a P-type dopant, and wherein implanting dopant of a second conductivity type comprises implanting an N-type dopant. 
     
     
         7 . The method of  claim 1 , further comprising introducing oxygen into the first doped region to form the at least one of nano-particles and nano-inclusions in the first doped region. 
     
     
         8 . The method of  claim 1 , further comprising introducing at least one rare-earth element into the first doped region. 
     
     
         9 . The method of  claim 8 , wherein introducing at least one rare-earth element comprises implanting at least one of erbium, praseodymium, and thulium. 
     
     
         10 . The method of  claim 1 , further comprising introducing inert dopant in the body to form an inert dopant region adjacent the second doped region and separate from the third doped region. 
     
     
         11 . The method of  claim 1 , further comprising forming sidewall spacers comprising a dielectric material adjacent sidewalls of the gate structure. 
     
     
         12 . The method of  claim 1 , further comprising connecting the third doped region to a source line. 
     
     
         13 . The method of  claim 1 , further comprising forming a silicide material over the third doped region. 
     
     
         14 . The method of  claim 13 , further comprising forming another silicide material over the second doped region. 
     
     
         15 . The method of  claim 14 , further comprising forming a thickness of the silicide material over the third doped region greater than a thickness of the another silicide material over the second doped region. 
     
     
         16 . The method of  claim 1 , further comprising growing epitaxial material on each of the second doped region and the third doped region to form a first raised region and a second raised region, the first raised region and the second raised region sharing a same horizontal spatial plane as a portion of the gate structure on a sidewall of the body. 
     
     
         17 . The method of  claim 16 , wherein growing epitaxial material on each of the second doped region and the third doped region comprises growing at least two different epitaxial materials on each of the of the second doped region and the third doped region. 
     
     
         18 . The method of  claim 1 , further comprising forming the first doped region separate from the gate structure and to comprise at least one rare-earth element. 
     
     
         19 . A method of forming a memory cell, comprising:
 forming a storage transistor at a surface of a substrate comprising:
 selectively removing material from the substrate to Ruin a body having a fin-like structure; 
 forming a gate structure wrapping around multiple surfaces of a portion of the body; 
 introducing dopant of a first conductivity type into the body at a position underlying and approximately aligned with an edge of the gate structure to form a first heavily doped region; 
 forming nano-particles in the first doped region; 
 introducing dopant of a second conductivity type into the substrate to form each of a second doped region comprising at least one of a source and drain region and a third doped region comprising at least one of an opposing source and an opposing drain region, the first doped region adjacent the third doped region and separated from the second doped region by an undoped region; 
 positioning the fin-like structure of the body between the first doped region and the second doped region; 
 connecting a bit line to the first doped region; and 
 connecting a word line to the gate structure. 
   
     
     
         20 . A method of forming a memory cell, comprising:
 selectively removing material from a substrate to form a body having a fin-like structure;   forming a gate structure wrapping around multiple surfaces of a portion of the body;   introducing dopant of a first conductivity type into the body at a position underlying and approximately aligned with an edge of the gate structure to form a first doped region separated from the gate structure and comprising at least one rare-earth element; and   introducing dopant of a second conductivity type into the substrate to form each of a second doped region comprising at least one of a source and drain region and a third doped region comprising at least one of an opposing source and an opposing drain region, the first doped region adjacent the third doped region and separated from the second doped region by an undoped region.