Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device

Abstract

A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate that includes a chip region, a scribe region that surrounds said chip region, and a pad region located in said scribe region and located in the vicinity of an edge of said semiconductor substrate in plan view;   a first conductive pattern formed on said substrate and located in said pad region and separated from said edge in plan view;   a second conductive pattern, that is electrically connected to said first conductive pattern and located in the vicinity of said edge, formed on said first conductive layer in said pad region.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprises:
 a third conductive pattern located in said pad region and located between said edge and said first conductive pattern in plan view,   wherein said second conductive pattern is formed on said first conductive pattern and said third conductive pattern.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein said third conductive pattern is separated from said edge. 
     
     
         4 . The semiconductor device according to  claim 2 , wherein said third conductive pattern is separated from said second conductive pattern. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein
 said pad region is defined by: a first outer peripheral part opposing said edge;   a second outer peripheral part reaching said edge and said first outer peripheral part;   and a third peripheral part reaching said edge and said first outer peripheral part, said pad region including a first apex formed by said first outer peripheral part and said second outer peripheral part, a second apex formed by said first outer peripheral part and said third outer peripheral part, and wherein said second conductive pattern is disposed adjacent to said first apex and said second apex.   
     
     
         6 . The semiconductor device according to  claim 1 , further comprising:
 a seal ring that surrounds said chip region and the seal ring is surrounded by said scribe region in plan view.   
     
     
         7 . The semiconductor device according to  claim 1 , wherein:
 an entirety of said second conductive pattern is located in said pad region in plan view.   
     
     
         8 . The semiconductor device according to  claim 1 , wherein:
 a first portion of said first conductive pattern is located in said pad region in plan view and a second portion of said first conductive pattern is located outside of said pad region in plan view.   
     
     
         9 . The semiconductor device according to  claim 1 , wherein:
 a first portion of said first conductive pattern is located in said pad region in plan view and a second portion is located outside of said pad region in plan view; and   an entirety of said second conductive pattern is located in said pad region in plan view.   
     
     
         10 . The semiconductor device according to  claim 1 , wherein:
 said first conductive pattern overlaps with said second conductive pattern in plan view.   
     
     
         11 . The semiconductor device according to  claim 1 , further comprising:
 a fourth conductive pattern formed on said semiconductor substrate in the pad region; and   a first via-plug formed on said fourth conductive pattern,   wherein said first conductive pattern is located on said first via-plug, and   said first via-plug is connected to said first conductive pattern and said fourth conductive pattern.   
     
     
         12 . The semiconductor device according to  claim 11 , further comprising:
 a second via-plug formed on said fourth conductive pattern,   wherein said first conductive pattern is located on said first via-plug and said second via-plug,   said first via-plug is connected to said first conductive pattern and said fourth conductive pattern, and   said second via-plug is connected to said first conductive pattern and said fourth conductive pattern.   
     
     
         13 . The semiconductor device according to  claim 11 , further comprising:
 a fifth conductive pattern formed on said semiconductor substrate in the pad region; and   a third via-plug formed on said fifth conductive pattern,   wherein said fourth conductive pattern is located on said third via-plug, and   said third via-plug is connected to said fourth conductive pattern and said fifth conductive pattern.   
     
     
         14 . The semiconductor device according to  claim 1 , wherein:
 said first conductive pattern includes copper; and   said second conductive pattern includes aluminum.   
     
     
         15 . The semiconductor device according to  claim 2 , wherein:
 said first conductive pattern includes copper;   said second conductive pattern includes aluminum; and   said third conductive pattern includes copper.   
     
     
         16 . The semiconductor device according to  claim 11 , wherein:
 said first conductive pattern includes copper;   said second conductive pattern includes aluminum;   said fourth conductive pattern includes copper; and   said first via-plug includes copper.   
     
     
         17 . The semiconductor device according to  claim 13 , wherein:
 said first conductive pattern includes copper;   said second conductive pattern includes aluminum;   said fourth conductive pattern includes copper;   said fifth conductive pattern includes copper;   said first via-plug includes copper; and   said second via-plug includes copper.   
     
     
         18 . The semiconductor device according to  claim 2 , further comprising
 a first insulation film formed on said semiconductor substrate; and   a second insulation film formed on said first insulation film,   wherein said first conductive pattern and said third conductive pattern are formed in said first insulation film, and   said second conductive pattern is formed in said second insulation film.