Apparatus and method for controlling controllable clock source to generate clock signal with frequency transition

Abstract

A clock generator includes a controllable clock source and a frequency hopping controller. The controllable clock source generates a clock signal to a clock-driven device. The frequency hopping controller controls the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition.

What is claimed is: 
     
         1 . A clock generator, comprising:
 a controllable clock source, configured to generate a clock signal to a clock-driven device; and   a frequency hopping controller, configured to control the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition.   
     
     
         2 . The clock generator of  claim 1 , wherein the clock-driven device is a memory device. 
     
     
         3 . The clock generator of  claim 2 , wherein the frequency hopping controller controls the controllable clock source to make the clock signal have the at least one frequency transition when a clock enable (CKE) control signal of the memory device is asserted. 
     
     
         4 . The clock generator of  claim 2 , wherein the frequency hopping controller controls the controllable clock source to make the clock signal have the at least one frequency transition when a clock enable (CKE) control signal of the memory device is de-asserted. 
     
     
         5 . The clock generator of  claim 1 , wherein the frequency hopping controller is configured to employ dynamic frequency scaling (DFS) to control the at least one frequency transition of the clock signal. 
     
     
         6 . The clock generator of  claim 1 , wherein the frequency hopping controller is configured to employ spread spectrum clocking (SSC) to control the at least one frequency transition of the clock signal. 
     
     
         7 . A clock generating method, comprising:
 utilizing a controllable clock source to generate a clock signal to a clock-driven device; and   controlling the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the at least one frequency transition is controlled to prevent the controllable clock source from leaving a frequency-locked state during a time period of the at least one frequency transition.   
     
     
         8 . The clock generating method of  claim 7 , wherein the clock-driven device is a memory device. 
     
     
         9 . The clock generating method of  claim 8 , wherein the step of controlling the controllable clock source to make the clock signal have the at least one frequency transition is performed when a clock enable (CKE) control signal of the memory device is asserted. 
     
     
         10 . The clock generating method of  claim 8 , wherein the step of controlling the controllable clock source to make the clock signal have the at least one frequency transition is performed when a clock enable (CKE) control signal of the memory device is de-asserted. 
     
     
         11 . The clock generating method of  claim 7 , wherein the step of controlling the controllable clock source to make the clock signal have the at least one frequency transition comprises:
 employing dynamic frequency scaling (DFS) to control the at least one frequency transition of the clock signal.   
     
     
         12 . The clock generating method of  claim 7 , wherein the step of controlling the controllable clock source to make the clock signal have the at least one frequency transition comprises:
 employing spread spectrum clocking (SSC) to control the at least one frequency transition of the clock signal.   
     
     
         13 . An electronic device, comprising:
 a memory controller, configured to control access of a memory device; and   a processor, configured to perform a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.   
     
     
         14 . The electronic device of  claim 13 , wherein the memory controller parameter is a data strobe (DQS) gating window. 
     
     
         15 . The electronic device of  claim 13 , wherein the memory controller parameter is a data latch (DATLAT) time. 
     
     
         16 . An electronic device, comprising:
 a processor, configured to perform a calibration operation to find a skew value between a data strobe (DQS) signal and a clock signal of a memory device; and   a clock generator, comprising:
 a controllable clock source, configured to generate the clock signal to the memory device; and 
 a frequency hopping controller, configured to control frequency hopping of the controllable clock source according to the skew value. 
   
     
     
         17 . The electronic device of  claim 16 , wherein the frequency hopping controller is configured to set a frequency transition from one clock frequency to another clock frequency according to the skew value, and control the controllable clock source to make the clock signal have the frequency transition. 
     
     
         18 . The electronic device of  claim 17 , wherein the frequency hopping controller is configured to employ dynamic frequency scaling (DFS) to control the frequency transition of the clock signal. 
     
     
         19 . The electronic device of  claim 17 , wherein the frequency hopping controller is configured to employ spread spectrum clocking (SSC) to control the frequency transition of the clock signal. 
     
     
         20 . The electronic device of  claim 16 , wherein the frequency hopping controller is configured to compare the skew value with a predetermined threshold, and disable the frequency hopping of the controllable clock source when a comparison result indicates that the skew value is larger than the predetermined threshold.