Belief propagation processor

Abstract

A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.

What is claimed is: 
     
         1 . A decoder comprising:
 a first memory for storing code data having a length in bits;   a second memory for storing intermediate data in analog form;   an analog decoder core coupled to the first memory and to the second memory, the decoder core having an input length less than the length of the code data and an output length less than a number of constraints represented in the code data;   a controller for, in each of a plurality of cycles, coupling the inputs of the decoder code to selected values from the first and the second memories, and coupling outputs of the decoder core for storage in the second memory; and   an output section coupled to the second memory for providing decoded data based on values stored in the second memory.   
     
     
         2 . The decoder of  claim 1 , wherein the first memory is configured for storing code data in analog form. 
     
     
         3 . A decoding method comprising:
 in each of a plurality of cycles of a decoding operation, applying a portion of code data and a portion of an intermediate value data to an analog decoder core, and storing an output of the decoder coder in an analog storage for the intermediate data; and   combining data, including intermediate value data from the analog storage, to form decoded data representing an error correction of the code data.   
     
     
         4 . The method of  claim 3  wherein each of the plurality of cycles is associated with a corresponding subset of less that all of a plurality of parity-check constraints of the code. 
     
     
         5 . The method of  claim 3  wherein the intermediate value data includes values each associated with a different one of the parity check constraints of the code.